Reset Sequencing

What this topic teaches

Reset Sequencing focuses on closing CDC/RDC risk with mechanism-level reasoning. Reset ordering enforces dependency contracts so control domains and memories become valid before downstream consumers execute. Senior signoff depends on proving behavior with targeted evidence, not just clearing tool warnings.

The senior-engineer question

When domain bring-up order violations, dependency deadlocks, reset latency regresses, can you classify the hazard, identify accountable owners, and choose the smallest fix or waiver backed by evidence?

CDC/RDC SIGNOFF FLOW — Reset Sequencing

crossing inventory + reset map
          |
          v
crossing classification (level/pulse/bus/reset)
          |
          v
structure + protocol + reset checks
          |
          v
critical issues + waiver review
          |
          v
fix / validate / regress / signoff

Picture the crossing behavior

Draw the behavior before touching tools. These visuals are the expected whiteboard baseline for reviews and interviews.

Reset dependency graph

always-on reset release
      -> clocks stable
      -> fabric/control release
      -> data-path release
      -> peripheral release

Violation causes boot races and phantom deadlocks.

Crossing sequence

CROSSING FLOW — Reset Sequencing

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: domain bring-up order violations, dependency deadlocks, reset latency

Ownership layers

CDC/RDC OWNERSHIP LAYERS — Reset Sequencing

layer                 owns                            common failure
------------------    -----------------------------   -----------------------------
design intent         crossing architecture           wrong topology selected
protocol semantics    req/ack, fifo, ordering        liveness/deadlock bugs
reset behavior        assert/deassert sequencing      boot instability
analysis setup        tool rules + waivers            false confidence
signoff governance    risk acceptance + dashboard     stale critical waivers

Evidence to collect

• Primary metric: domain bring-up order violations, dependency deadlocks, reset latency.

• Primary artifact: bring-up sequence spec, dependency matrix, firmware reset script.

• Owners to involve: SoC integration owner, firmware owner, RTL lead.

• At least one reproducer tied to mode/reset/traffic context.

• Decision record: fix, waive, or escalate with rationale.

Ownership map

OWNERSHIP MAP — Reset Sequencing

artifact                  owner
----------------------    -------------------------
design intent           SoC integration owner
verification evidence   firmware owner
signoff decision        RTL lead

Every open CDC/RDC issue needs one accountable owner before waiver or fix.

Subpages in this topic

Each topic includes mechanism, I/O contract, metrics, debug, worked example, pitfalls, interview drills, checklist, theory, design tradeoffs, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• Classify crossing/reset hazards before proposing fixes.

• Pair structural results with protocol/reset behavioral proof.

• Treat waivers as bounded risk contracts, not cleanup shortcuts.

Common pitfalls

• Mass-waiving warnings near tapeout.

• Assuming local IP cleanliness guarantees SoC behavior.

• Skipping reconvergence and reset stress after CDC fixes.

CDC/RDC deep dive

Reset release ordering is a first-order reliability contract.

Concept diagram

RESET RELEASE FLOW

assert global -> clocks stable -> sync release per domain -> first transaction

Metric graph

BOOT STABILITY

passes per 1k boots: 920 -> 980 -> 999

Reports and artifacts

• reset dependency matrix

• RDC warning classes

• boot stress logs

• waiver aging

Mini case study

Domain B released before producer A was valid, causing rare startup deadlock.

Debug branches

• Correlate reset and clock timelines

• verify async assert/sync release

• exercise skewed release tests

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.