Two release mistakes cause most reset-domain failures at signoff. The first is releasing the domain straight from the asynchronous source, which the earlier lessons cover. The second is passing the reset through combinational logic on its way to the flops, for example gating it with an enable or a mode bit. Both give some flops a different release time than others.
// bad-example
// Gating a reset with logic: the enable glitch re-asserts reset mid-operation,
// and the gate delays the release differently per load.
assign domain_rst_n = arst_n &_block_enable;Combinational logic on a reset net has two effects. A glitch on any input re-asserts reset in the middle of normal operation, which the design experiences as a spurious partial reset. And even without glitches, differing path delays stagger the release across flops, recreating the inconsistent wake-up of an unsynchronised release.
The waveform below is simulation output for a simple deterministic model of two flops sharing one raw asynchronous reset. The model is deliberately simple, and it is stated here exactly: if the release lands within 1.5 ns before a clock edge, one flop wakes up at that edge and the other holds its reset value for one more cycle; a mid-cycle release wakes both together. Real silicon resolves nondeterministically; the model stands in for that with a fixed pattern so the waveform is reproducible.
How to read it: the clock has a 10 ns period with rising edges at 5, 15, 25 ns and so on, one slot per edge. The reset asserts at 2 ns, releases at 34 ns (1 ns before the edge at 35 ns), re-asserts at 50 ns, and releases cleanly mid-cycle at 60 ns.
Slots 0 to 2: reset asserted, both flops held at 0.
Slot 3: the near-edge release. One flop (q_a) wakes to 1 while the other (q_b) still holds 0: the two flops disagree for a cycle.
Slot 4: the late flop catches up and both read 1.
Slot 5: re-assertion clears both together; slots 6 to 7 show the clean mid-cycle release waking both at once.
The slot-3 disagreement is the whole hazard in one picture: identical flops, identical reset, different wake-up times, and any state machine built from them starts in a state nobody designed.
Slot 3: q_a is 1 while q_b is still 0. The release at 34 ns landed 1 ns before the clock edge, inside the model's window, so the flops woke a cycle apart.
The gate adds its own delay and glitch risk after the synchroniser: different flops see the release at different times, and a glitch re-asserts reset mid-operation. The synchronised edge is wasted if logic reshapes it afterwards.