A spurious reset pulse and a glitchy release look identical downstream: flops cleared mid-operation, protocol state torn, symptoms far from the cause. The debugging question is always where the edge came from: the genuine source asserting, logic on the reset net reshaping it, or a release landing inside a recovery/removal window.
This lesson reuses the release waveform from the deassertion topic (imported from the same generated waves file, not a second copy). Read it again here with debugger's eyes: the point is what distinguishes a clean release from a hazardous one on the lanes.
How to read it for debug: the clock has a 10 ns period with rising edges at 5, 15, 25 ns and so on, one slot per edge. The reset asserts at 2 ns, releases at 34 ns (1 ns before the edge at 35 ns), re-asserts at 50 ns, and releases cleanly mid-cycle at 60 ns.
Slots 0 to 2 show the asserted baseline: both flops at 0. Any slot where a flop reads 1 while reset is asserted means the reset never reached it.
Slot 3 is the smoking gun for release timing: q_a at 1 with q_b still at 0 after the same release edge. Two identical flops disagreeing for exactly one cycle is the signature of a near-edge release, not of a data bug.
Slots 6 to 7 show the control case: the mid-cycle release wakes both together. If a suspect release produces this shape, timing is innocent and the search moves to gating logic or the source.
If the disagreement shape appears and moves with the release instant (present at some instants, absent at others), the release path is asynchronous: add or repair the synchroniser.
If a short assertion appears that no source drove, probe the reset net for combinational inputs: an enable or mode bit changing mid-operation re-asserts through the gate.
If the source itself pulsed, the fix is at the source (debounce, qualify, or hold the condition), not in the receiving domain.
Release timing: the first instant lands in a recovery/removal window while the shifted one does not. The release needs a synchroniser; the data path is fine.
At combinational logic on the reset net between source and flops: a changing enable or mode input is re-asserting reset through the gate. Remove the logic.