When a reset-domain bug bites, the fastest route to the cause is the symptom. Each classic symptom points at a small set of reset mechanisms; checking those first beats re-reading the data path. Confirm the guess with the smallest test that reproduces it, usually a reset at a chosen instant rather than a full rerun.
Symptom | Likely reset cause | First check |
|---|---|---|
X after reset in simulation or on the bench | A flop or memory with no reset, or a reset that never reached it (gated clock off, missing synchroniser output) | Trace the X source back to its reset net; check the flop is on a live reset |
One block stuck while neighbours run | Block still in reset (sequencer never released it, lost lock re-asserted), or waiting on a peer's ready flag | Read back the block's reset and ready flags; check the sequencer order |
Sporadic failure just after release, never the same twice | Release violating recovery/removal on some boots; raw or gated release path | Inspect the release path for a synchroniser and combinational logic; sweep the release instant |
State loss on warm reset (config gone, link dead) | Warm reset clearing registers it should preserve, or keeping protocol state the partner forgot | Diff the cleared-versus-preserved list against the spec for that reset kind |
Duplicate or stale words after a one-sided reset | Interrupted handshake without protocol tolerance; reset values sampled as data | Check isolation plus the armed/qualify logic on the crossing |
Notice the pattern: the first two symptoms are about reset not doing its job (reach and order), the next two about reset doing too much or at the wrong time (release timing, over-clearing), and the last about the crossing protocol meeting a reset halfway. Naming which of the three classes the symptom belongs to halves the search space before any waveform is opened.
Over-clearing: the warm reset clears registers it should preserve. Compare the reset's cleared-versus-preserved list against the spec for warm reset.
The release path: look for a missing synchroniser or combinational logic on the reset net, then sweep the release instant to confirm the timing dependence.