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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
    • Reset Deassertion CDC
    • Reset Sequencing
      • Release Order Across Domains
      • Reset Isolation
      • Async Reset Into Sync Logic
      • Power-On and Warm Reset
    • RDC Structural Checks
    • Reset Debug Playbook
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Reset Sequencing
  1. Topics
  2. CDC & RDC
  3. Reset Domain Crossing
  4. Reset Sequencing
  5. Async Reset Into Sync Logic

Part 5 · Reset Domain Crossing · All levels

Async Reset Into Sync Logic

Asynchronous resets feeding logic in other domains and the crossings that result.

Resets rarely stay inside one domain. A watchdog in one clock domain resets logic in another, software writes a reset bit that fans out across domains, and a reset status flag generated in one domain is read as an ordinary input elsewhere. Every one of these is a crossing: a signal whose timing is unrelated to the clock of the logic it drives.

The hazard depends on how the receiving logic uses the reset. Used as a true asynchronous clear on flops of its own domain, it needs the usual synchronised release from the earlier topic. Used as anything else, a data input, an enable, a condition in combinational logic, it is a plain unsynchronised crossing with all the usual failure modes: a glitch asserts reset spuriously, a slow edge lingers, and different loads see the change in different cycles.

How the foreign reset is used

Hazard

Treatment

Asynchronous clear of the receiving domain's flops

Unsafe release timing

Route through that domain's reset synchroniser

Read as a status or data input

Metastability at the sampling flop

Synchronise it like any control crossing first

Combined into enables or combinational conditions

Glitches and staggered arrival across loads

Synchronise, then use the clean version; never gate raw

design.sv
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// bad-example
// A reset from another domain used as ordinary logic: glitch-prone,
// untimed, and seen differently by each load.
always_ff @(posedge clk_b)
  if (!wdog_rst_from_a) state <= IDLE;
  else                  state <= next_state;

The corrected version passes the watchdog reset through domain B's own reset synchroniser (or a control synchroniser if it is genuinely a status input) and uses only the clean result. The raw net from the other domain touches nothing else.

Common pitfall

Software-driven resets are the most frequently missed case: a register bit written by firmware looks like ordinary control, but it changes asynchronously to every clock it reaches. Every software reset needs the same synchronised treatment as a pin reset.

Check yourself A watchdog reset generated in domain A clears flops in domain B directly. Name the two hazards.

Release timing in domain B (recovery/removal against clk_b), and the assertion edge arriving asynchronously to anything in B that samples around it. Domain B needs its own synchronised copy.

Check yourself When is it acceptable for a foreign reset to feed combinational logic directly?

Never for a reset that is foreign to the receiving domain: synchronise it into that domain first, then use the clean copy. Raw cross-domain nets touch nothing but synchroniser inputs.

Related topics

  • Power-on and warm reset

  • RTL: Synchronizers

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See also

  • Release Order Across Domains