Reset synchronisers align each release to its own clock, but they say nothing about the order in which domains wake up. Two domains can each release perfectly and still be incompatible for several cycles: the producer is already sending while the consumer's flops are still held in reset, so the first words land nowhere.
The general rule is receivers before senders. A consumer must be out of reset, with its handshake or FIFO pointers in their idle state, before its producer starts traffic. Memory controllers come up before the CPUs that use them; clock-status logic comes up before anything that depends on the clock being stable. The full power-up sequence, including the PLL-lock wait, is worked through in Reset Architecture.
A reset sequencer releases domain resets in dependency order with gaps between them, so each block is stable before the next starts.
Ready flags between blocks: each block announces it has left reset and is idle, and no block starts traffic until its peer's flag is set.
Software-gated start: the last step of the sequence enables traffic explicitly rather than letting each block free-run out of reset.
Same-cycle on unrelated clocks is not simultaneous, and nothing guarantees the consumer's idle state is established before the producer sends. Order plus a ready flag is needed, not just synchronised releases.
A reset sequencer that staggers the releases in dependency order, and ready flags so no block starts traffic before its peer announces it is out of reset and idle.