The toggle scheme is the standard answer when a pulse is too short for the destination clock. It converts the event into a level change that persists for as long as needed, so the destination is guaranteed a stable level to sample. Every signoff reviewer recognises the three-part shape: a source toggle flop, a level synchroniser, and a destination edge detector.
Source: a flop that flips on every input pulse (toggle_s <= ~toggle_s). Each event becomes a level change that holds until the next event.
Crossing: a two-flop (or more) synchroniser on the destination clock carries the level, exactly like any single-bit level crossing.
Destination: an edge detector (pulse_d = sync ^ sync_delayed) turns each received flip back into a one-cycle pulse.
// snippet: the toggle scheme in compact form (resets omitted for brevity;
// the full resettable version is built in the RTL handshake lessons).
// Source domain:
// always @(posedge clk_s) if (pulse_s) toggle_s <= ~toggle_s;
// Crossing: 2FF synchroniser of toggle_s into clk_d -> sync_t.
// Destination domain:
// always @(posedge clk_d) sync_t_d <= sync_t;
// assign pulse_d = sync_t ^ sync_t_d;The waveform below is simulation output for the wave source of this topic: a one-cycle source pulse beside the same event sent as a toggle. One slot is one cycle of clk_s.
How to read it: pulse_s is high for a single source slot (slot 2), between two destination edges, so a plain synchroniser would never see it. toggle_s flips in slot 5 and holds still. sync_t rises in slot 10, two destination edges later, and the edge detector answers with pulse_d high across slots 10 to 12 and low again in slot 13.
The source must not toggle again before the destination has seen the current toggle. If two flips land inside one destination period, the synchroniser output may move once or not at all, and one event is lost. The enforceable form of the rule is a minimum spacing between source pulses, covered in the spacing lesson.
Review question | What passes |
|---|---|
Is the toggle flop clocked by the source clock and fed only by the pulse? | Yes, with no combinational shortcuts around it |
Does the level cross through a proper synchroniser? | Two or more destination flops, no logic between them |
Is the edge detector on the synchronised output, not the raw toggle? | Only the last synchroniser flop feeds the XOR |
Is the spacing rule written down and checked? | A stated minimum gap plus an assertion or test (see the spacing lesson) |
The flips are 15 ns apart but the destination period is 20 ns, so both flips can fall inside one destination period and merge: the destination may report one pulse or none. The spacing rule is violated.