Toggling is not the only way to make a pulse wide enough to sample. Holding the pulse high for a fixed number of source cycles (stretching) is simpler to build and simpler to review, and for slow event sources it is completely adequate. A signoff reviewer needs to know both schemes and, more importantly, when stretching stops being acceptable.
A stretch counter in the source domain holds the event high for S source cycles. The destination synchronises the resulting wide level through a two-flop synchroniser and edge-detects it, exactly as in the toggle scheme, producing one destination pulse per stretched event.
// snippet: stretch an event to S source cycles, then synchronise as a level.
// Source domain:
// always @(posedge clk_s) begin
// if (pulse_s) stretch <= S; else if (stretch != 0) stretch <= stretch - 1;
// level_s <= (pulse_s || stretch != 0);
// end
// Crossing: 2FF synchroniser of level_s into clk_d, then XOR edge detect.Question | Toggle scheme | Stretch scheme |
|---|---|---|
What crosses the boundary | A level that flips per event | A level held high for S source cycles |
Source state needed | One toggle flop | A counter plus the level flop |
Destination output per event | Exactly one pulse | Exactly one pulse, via the same edge detector |
Needs the spacing rule | Yes: flips must stay apart | Yes: stretched pulses must not overlap |
Failure if misconfigured | Merges events silently | A too-short stretch is missed silently |
Stretching is acceptable when the stretched width S is chosen against the destination period with margin (at least two destination periods, preferably more) and the destination clock rate is bounded: if the destination can be slowed by a power mode, a fixed S can become too short. Toggling has no such dependence, because the level holds until the next event however slow the destination is.
Both schemes share the destination side: synchronise the level, delay it one cycle, XOR. The output pulse is one destination cycle wide. A reviewer checks that the detector watches the synchronised level and that nothing downstream expects the pulse to arrive in any fixed number of source cycles: the latency is two to three destination cycles plus synchroniser settling, never a source-cycle count.
Marginally: 40 ns covers at most two edges and a phase shift can leave only one usable sample. Widen to at least 50 ns (two full periods) with margin, or use a toggle.