Async FIFO CDC

What this topic teaches

Async FIFO CDC focuses on closing CDC/RDC risk with mechanism-level reasoning. Async FIFOs decouple domains with gray-coded pointers and synchronized status logic; correctness depends on pointer math, full/empty rules, and reset behavior. Senior signoff depends on proving behavior with targeted evidence, not just clearing tool warnings.

The senior-engineer question

When overflow/underflow risk, pointer synchronization integrity, latency throughput regresses, can you classify the hazard, identify accountable owners, and choose the smallest fix or waiver backed by evidence?

CDC/RDC SIGNOFF FLOW — Async FIFO CDC

crossing inventory + reset map
          |
          v
crossing classification (level/pulse/bus/reset)
          |
          v
structure + protocol + reset checks
          |
          v
critical issues + waiver review
          |
          v
fix / validate / regress / signoff

Picture the crossing behavior

Draw the behavior before touching tools. These visuals are the expected whiteboard baseline for reviews and interviews.

Async FIFO core

write clk domain                       read clk domain
wr_ptr(bin->gray) ---sync---> rd domain compare
rd_ptr(bin->gray) <---sync--- wr domain compare

full/empty must be computed with synchronized gray pointers.

Crossing sequence

CROSSING FLOW — Async FIFO CDC

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: overflow/underflow risk, pointer synchronization integrity, latency throughput

Ownership layers

CDC/RDC OWNERSHIP LAYERS — Async FIFO CDC

layer                 owns                            common failure
------------------    -----------------------------   -----------------------------
design intent         crossing architecture           wrong topology selected
protocol semantics    req/ack, fifo, ordering        liveness/deadlock bugs
reset behavior        assert/deassert sequencing      boot instability
analysis setup        tool rules + waivers            false confidence
signoff governance    risk acceptance + dashboard     stale critical waivers

Evidence to collect

• Primary metric: overflow/underflow risk, pointer synchronization integrity, latency throughput.

• Primary artifact: FIFO architecture diagram, pointer proof checks, formal safety properties.

• Owners to involve: RTL owner, CDC owner, formal owner.

• At least one reproducer tied to mode/reset/traffic context.

• Decision record: fix, waive, or escalate with rationale.

Ownership map

OWNERSHIP MAP — Async FIFO CDC

artifact                  owner
----------------------    -------------------------
design intent           RTL owner
verification evidence   CDC owner
signoff decision        formal owner

Every open CDC/RDC issue needs one accountable owner before waiver or fix.

Subpages in this topic

Each topic includes mechanism, I/O contract, metrics, debug, worked example, pitfalls, interview drills, checklist, theory, design tradeoffs, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• Classify crossing/reset hazards before proposing fixes.

• Pair structural results with protocol/reset behavioral proof.

• Treat waivers as bounded risk contracts, not cleanup shortcuts.

Common pitfalls

• Mass-waiving warnings near tapeout.

• Assuming local IP cleanliness guarantees SoC behavior.

• Skipping reconvergence and reset stress after CDC fixes.

CDC/RDC deep dive

Protocol correctness is the bridge between structural clean and functional safe.

Concept diagram

PROTOCOL FLOW

intent -> transport protocol -> synchronization -> destination acceptance

Metric graph

PROTOCOL ISSUE BURNDOWN

open issues: 20 -> 11 -> 5 -> 0

Reports and artifacts

• FIFO pointer proofs

• req/ack liveness

• pulse miss checks

• protocol assertions

Mini case study

Async FIFO empty/full logic looked correct until gray decode mismatch appeared during reset overlap.

Debug branches

• Pointer sync audit

• formal liveness checks

• reset interaction review

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.