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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
    • Pulse Synchronizers
    • Handshake Protocols Across Domains
    • Async FIFO CDC
      • Gray Pointers in Signoff
      • Full and Empty
      • Depth Sizing
      • FIFO Reset and Tool Checks
    • CDC Protocol Verification
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Async FIFO CDC
  1. Topics
  2. CDC & RDC
  3. CDC Protocols and Handshakes
  4. Async FIFO CDC
  5. Depth Sizing

Part 3 · CDC Protocols and Handshakes · All levels

Depth Sizing

Sizing FIFO depth from burst length, write/read rates and synchroniser latency, with a symbolic example.

On this page

    Why it matters

    An undersized FIFO is a functional bug with a long fuse: it passes every short test and overflows on the first long burst in the system. Depth is therefore a signoff calculation, written in the design document with its inputs named, not a power-of-two guess. The three inputs are the burst length, the rate mismatch during the burst, and the synchroniser latency hiding recent reads and writes.

    The sizing argument

    During a burst the writer outruns the reader and occupancy grows by the rate difference accumulated over the burst. On top of that, each side works from a stale view of the other pointer, so a few extra entries cover the in-flight synchroniser delay. Almost-flag margins for pipeline reaction time add further entries where the producer cannot stop instantly.

    Symbolic worked example (illustrative)

    All numbers below are illustrative: a burst of B = 120 words, write rate twice the read rate, and a synchroniser and flag latency worth about 2 entries each way.

    Diagram
    illustrative depth sizing, recomputed two ways (B = 120 words, fw:fr = 2:1)
    method 1, rate difference:
      accumulated = B x (1 - fr / fw) = 120 x (1 - 1/2) = 60 words
      synchroniser margin = 4 entries (about 2 entries per direction for the synchroniser and flag latency)
      total = 60 + 4 = 64 -> next power of two: 64
    method 2, time based (same inputs, counting from the burst duration):
      burst lasts 120 write cycles = 60 read cycles; reads remove 60 words
      net stored = 120 - 60 = 60 words; plus 4 margin = 64 -> depth 64
    both countings agree: 64 entries

    Input

    Where it comes from

    If it is unknown

    Burst length B

    The protocol or the producer's maximum burst

    Measure the longest burst in system simulation; do not guess

    Rate ratio fw:fr

    Clock frequencies and the producer/consumer duty cycles

    Assume the worst supported combination

    Synchroniser margin

    Synchroniser stages plus flag pipeline depth

    Allow at least 2 entries per crossing direction

    What the checks look for

    Reviewers ask for the sizing calculation and its three inputs, then check the testbench covers the worst case: a full-length burst at the worst rate ratio with the consumer stalled at the start. A FIFO that is only ever tested half-full is not signed off.

    Common mistakes

    Common pitfall

    Sizing for the average rate instead of the burst. Averages say the FIFO never fills; bursts say it fills every time. Size for the burst, and provide back-pressure (full) for the case where bursts exceed even that.

    Interview

    Walk through the worked example, then volunteer the re-check: recompute from burst duration the other way round. Interviewers remember candidates who verify their own arithmetic.

    Check yourself A burst holds 80 words with fw:fr = 4:1 and a synchroniser margin of 4. What depth?

    Accumulated 80 x (1 - 1/4) = 60, plus 4 = 64 entries. Recompute by time: the burst lasts 80 write cycles = 20 read cycles, reads remove 20, net 60, plus 4 = 64. Both agree.

    Related topics

    • Full and empty

    • Latency and throughput

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    See also

    • Gray Pointers in Signoff