Valid/ready is the lingua franca of on-chip interfaces, so designers constantly ask whether a valid/ready pair can simply be wired across a clock boundary. The signoff answer is no: the protocol assumes source and destination sample the same values in the same cycle, which is exactly what a clock boundary does not guarantee. Crossing needs a wrapper that restores that assumption on each side.
A valid/ready transfer completes in the cycle both are high. Across clocks, valid from the source may be sampled as high in one destination cycle and low in the next while the source still means the same transfer; ready returning the other way has the same problem. The two sides can then disagree about whether a transfer happened: the source counts it, the destination never saw it, or the destination counts it twice. There is no single-bit synchroniser arrangement that fixes this, because the protocol's correctness depends on agreed single-cycle simultaneity.
Wrapper | What it does | Use when |
|---|---|---|
Four-phase (or two-phase) handshake around the word | Carries each transfer as an event with an acknowledge | Occasional words: configuration, commands, status |
Async FIFO with valid/ready facades | Source pushes on valid, destination pops to ready; full/empty become the back-pressure | Streams and bursts at any sustained rate |
Request/acknowledge with credit counting | Destination pre-grants N transfers; source counts down without waiting | Steady streams where round-trip latency would stall |
Keep valid/ready as the interface on each side, and put the clock boundary inside a wrapper: the source side accepts the word with its own synchronous valid/ready timing, the crossing (handshake or FIFO) moves it, and the destination side offers it with destination-clock valid/ready timing. Each side then sees an ordinary same-clock protocol, and the crossing inside is one of the reviewed structures from this section.
A structural analysis generally flags any valid or ready signal crossing a domain without a handshake or FIFO wrapper as an unsynchronised or protocol-violating crossing. A reviewer asks where the boundary sits inside the wrapper and confirms that no ready path is combinational across the boundary: a combinational ready from the far clock domain reintroduces the simultaneity assumption the wrapper was meant to remove.
First, the synchronised valid is delayed by two to three destination cycles, so source and destination disagree on which cycle the transfer happened in. Second, the combinational return of ready across the boundary is itself an unsynchronised crossing that can glitch or go metastable.