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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
    • Pulse Synchronizers
    • Handshake Protocols Across Domains
    • Async FIFO CDC
    • CDC Protocol Verification
      • Assertions for Protocols
      • Formal Protocol Checks
      • Coverage and Stress
      • Metastability-Aware Simulation
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹CDC Protocol Verification
  1. Topics
  2. CDC & RDC
  3. CDC Protocols and Handshakes
  4. CDC Protocol Verification
  5. Coverage and Stress

Part 3 · CDC Protocols and Handshakes · All levels

Coverage and Stress

Stall, back-pressure and rate-mismatch scenarios with a coverage checklist.

On this page

    Why it matters

    Protocol bugs cluster where the two sides disagree about pace: the producer stalls, the consumer applies back-pressure, or the rate ratio sits at its most awkward corner. A test plan that only runs smooth, matched-rate traffic will miss all of them. Stress scenarios plus a coverage checklist turn pace disagreement from an accident into a planned exercise.

    Scenario set

    Scenario

    What it does

    What it exposes

    Producer stall mid-burst

    Source stops offering for a random stretch, then resumes

    Handshake hangs, FIFO drains, almost-empty handling

    Consumer back-pressure

    Destination refuses transfers (ready low, rinc off) for long spells

    Full handling, producer overflow, almost-full reaction time

    Rate mismatch extremes

    Fast-to-slow and slow-to-fast at the worst supported ratio

    Lost pulses, flag latency, throughput shortfall

    Reset mid-transfer

    One or both resets asserted with req high or the FIFO part-full

    Stuck handshake, half-reset pointers

    Back-to-back minimum-gap events

    Pulses at exactly the stated minimum spacing

    Spacing guard off-by-one errors

    Clock phase drift

    Nearly equal frequencies so alignment sweeps all phases

    Phase-dependent sampling bugs

    Coverage checklist

    Cover

    Sign-off criterion

    Every protocol state and transition

    Each handshake state visited, each FIFO flag asserted at least once

    Full and empty reached

    FIFO genuinely full and genuinely empty during the run, not just nearly

    Minimum-gap traffic

    Events at the minimum spacing, plus one deliberately shorter (negative test)

    Stall and back-pressure durations

    Stalls longer than the deepest pipeline plus synchroniser latency

    Reset during activity

    Reset asserted in each protocol phase, recovery checked

    Mutation sensitivity

    A deliberately broken variant (binary pointers, unstable data, short hold) fails the same plan

    Common mistakes

    Common pitfall

    Counting coverage from a run where the FIFO never filled. Transition coverage of the full flag means nothing if full never asserted; check the flags reached, not just that their logic was visited.

    Check yourself The plan covers all handshake states but reset was only applied while idle. What is missing?

    Reset during an active transfer in each phase: stuck req or ack, and the recovery sequence back to the idle state on both sides.

    Related topics

    • Assertions for protocols

    • Metastability-aware simulation

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    See also

    • Assertions for Protocols