CDC / RDC · All levels

MTBF & Synchronizer Math: Interview Drills

Interview Drills for MTBF & Synchronizer Math.

Interview drills

Interview Drills for MTBF & Synchronizer Math focuses on MTBF target vs product FIT budget, synchronizer latency budget. The goal is to convert issue observations into mechanism-backed closure decisions.

diagram
PROMPT
You see MTBF target vs product FIT budget, synchronizer latency budget in MTBF & Synchronizer Math. Explain root cause and signoff decision.

STRONG ANSWER
1. Names crossing/reset class and context.
2. Explains Metastability cannot be eliminated, only pushed beyond mission lifetime by adequate settle time, stage count, and frequency-aware design.
3. Requests MTBF worksheet, synchronizer cell characterization, frequency assumptions.
4. Chooses fix/waiver/escalation with regression plan.

WEAK ANSWER
Lists tool commands or generic advice without mechanism and risk framing.

Diagram to draw on whiteboard

MTBF intuition

diagram
METASTABILITY MODEL

clock edge samples async input near transition
  -> first flop may metastabilize
  -> settle window before second flop sample

More settle time + better tau => higher MTBF.

Debug tree to narrate

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ROOT-CAUSE TREE — MTBF & Synchronizer Math

crossing failure observed
        |
   reproducible?
     /        \
   no          yes
   |            |
stress mode   classify issue
expansion       /      |      \
            synchronizer protocol reset/reconvergence
                 |         |           |
            MTBF fit    liveness    release ordering

CDC/RDC deep dive

Metastability is managed risk, not eliminated risk.

Concept diagram

diagram
METASTABILITY FLOW

async event -> first sample may metastabilize
 -> settle window
 -> downstream sample confidence

Metric graph

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MTBF TREND

target MTBF ---------
current design   ____/

Reports and artifacts

  • MTBF assumptions

  • synchronizer inventory

  • crossing class summary

  • critical waivers

Mini case study

Pulse sync chosen for a level signal caused intermittent stuck state under voltage stress.

Debug branches

  • Validate crossing class first

  • Check pulse width assumptions

  • Audit synchronizer template usage

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

  • State crossing class, assumptions, and owner with every issue.

  • Run structural and dynamic regressions after each fix.

Common pitfalls

  • Treating all warnings as equivalent risk.

  • Waiving issues without containment evidence.

  • Skipping reset and reconvergence stress after CDC fixes.

Principal CDC/RDC review addendum

Metastability cannot be eliminated, only pushed beyond mission lifetime by adequate settle time, stage count, and frequency-aware design.

Metric: MTBF target vs product FIT budget, synchronizer latency budget