This example works the MTBF model end to end so you can see which term does the work. Every parameter below is made up for teaching and labelled illustrative: never carry these numbers into a real design, where τ and T_W come from the library.
Parameter | Illustrative value |
|---|---|
Destination clock f_clk | 500 MHz (period T = 2.0 ns) |
Data rate f_data | 50 MHz (one change per 10 clocks on average) |
Flop time constant τ | 20 ps |
Window T_W | 100 ps |
Overhead (clock-to-Q plus next-stage setup) | 0.2 ns |
Resolution time t_r (two stages) | 2.0 − 0.2 = 1.8 ns = 1800 ps |
ILLUSTRATIVE worked example: parameters above are made up for teaching
exponent = t_r / tau = 1800 ps / 20 ps = 90
e^90 = 10^(90 x 0.4343) = 10^39.09 = 1.22 x 10^39
vulnerable-event rate = T_W x f_clk x f_data
= 1e-10 s x 5e8 /s x 5e7 /s = 2.5e6 /s
MTBF = 1.22e39 / 2.5e6 = 4.9e32 s
= 4.9e32 / 3.15e7 s/year = 1.5e25 yearsRecompute as a failure rate to check: e^(−90) is 8.2 × 10^(−40), times 2.5 × 10^6 per second gives 2.05 × 10^(−33) failures per second, whose reciprocal is 4.9 × 10^32 seconds. Both directions agree.
A third flop adds one more destination period of resolution time: 2.0 ns, or 2000 ps, which is 100 more τ. The exponent grows from 90 to 190, so MTBF is multiplied by e^100, about 2.7 × 10^43, reaching roughly 1.3 × 10^76 seconds.
The lesson is qualitative, and it is the whole point of the exercise: the extra clock period of settling time enters the exponent, so each added stage multiplies MTBF by an astronomically large factor rather than adding a small margin. No real device figure is claimed here.
About 7.5e24 years: half. The data rate is linear in the denominator, so doubling it halves MTBF and nothing else moves.
It adds one destination clock period of latency, usually negligible, while multiplying MTBF by e^(T/τ), an enormous factor. Reliability per unit latency is the best trade in CDC design.