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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
    • Reset Deassertion CDC
    • Reset Sequencing
    • RDC Structural Checks
      • What Is an RDC Crossing
      • RDC Categories
      • Reset Ordering Violations
      • Reading RDC Findings
    • Reset Debug Playbook
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹RDC Structural Checks
  1. Topics
  2. CDC & RDC
  3. Reset Domain Crossing
  4. RDC Structural Checks
  5. What Is an RDC Crossing

Part 5 · Reset Domain Crossing · All levels

What Is an RDC Crossing

A signal launched from logic reset by one reset and captured by logic with another, and why the source reset's assertion can corrupt the capture.

A reset-domain crossing is a signal path whose launching flop and capturing flop sit under different resets. The clocks may even be the same: if the source can be reset while the destination keeps running, the path is an RDC crossing regardless of the clocks involved.

The corrupting event is the assertion of the source reset, and it needs no clock subtlety to do damage. When the source domain resets, its flops jump to their reset values at an arbitrary moment. A destination flop that samples the crossing around that moment captures a value mid-transition: part old state, part reset value. Even away from any edge, the destination keeps sampling the source's reset values as if they were live data, which is the reset-value leakage the isolation lesson guards against.

Situation

Is it an RDC crossing?

Why

Same clock, different resets, signal passes between

Yes

Source reset can fire while the destination runs

Different clocks, one shared reset released through per-domain synchronisers

Still needs review

Releases land cycles apart; ordering and protocol tolerance still apply

Different clocks, different resets

Yes, and usually also a CDC crossing

Both the clock and the reset relationships need protection

Same clock, same reset everywhere on the path

No

No reset can fire on one side only; ordinary timing applies

Common pitfall

“Same reset pin” does not mean “same reset domain”. The pin reaches each domain through its own synchroniser and distribution, so the domains release cycles apart and can be re-asserted separately by gated or conditional logic. Trace the actual reset net to each flop, not the pin name.

Interview

“What is RDC in one sentence?” Failures caused by a reset firing on one side of a signal path while the other side keeps running: corrupted capture at assertion, reset values mistaken for data, and protocol state that disagrees afterwards.

Check yourself Source and destination share a clock but have independent resets. Is a data path between them an RDC crossing?

Yes. Either reset can fire while the other side runs, so assertion timing, reset-value leakage, and release ordering all apply despite the shared clock.

Check yourself Why is the assertion edge, not just the release, a hazard on an RDC crossing?

Assertion changes the source flops' outputs at an arbitrary moment, so a destination sampling nearby captures a mid-transition value, and afterwards it keeps capturing reset values as though they were data.

Related topics

  • RDC categories

  • RTL: Reset Domain Crossing

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See also

  • Reset Ordering Violations
  • Reading RDC Findings