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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
    • Reset Deassertion CDC
    • Reset Sequencing
    • RDC Structural Checks
      • What Is an RDC Crossing
      • RDC Categories
      • Reset Ordering Violations
      • Reading RDC Findings
    • Reset Debug Playbook
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹RDC Structural Checks
  1. Topics
  2. CDC & RDC
  3. Reset Domain Crossing
  4. RDC Structural Checks
  5. RDC Categories

Part 5 · Reset Domain Crossing · All levels

RDC Categories

Generic categories of reset-crossing findings: what each means and the typical fix.

A structural analysis reports reset crossings in a handful of recurring shapes. The names below are generic categories, not any tool's messages, and each maps to a standard fix. Learning the shapes matters more than learning any report format: the same five shapes appear in every design.

Category

Meaning

Typical fix

Different reset on source and capture

Launching and capturing flops sit under different resets with no protection between them

Add a synchroniser, isolation, or a coordinated reset; justify the choice

No synchroniser on the release path

A domain's reset is released straight from an asynchronous source

Insert a per-domain reset synchroniser

Reset used as data or control

A reset net (or a flop it drives) feeds data, enable, or combinational logic in another domain

Synchronise into the receiving domain first; use only the clean copy

Partial or conditional reset

Some flops on a path reset while others do not, or reset depends on a mode bit

Reset the whole protocol group together, or prove the unreset flops cannot affect the crossing

Combinational logic on the reset net

Gates or muxes sit between the reset source and the flops

Remove the logic; the synchroniser output reaches flops unmodified

The ordering is deliberate: the first row is the most common and the fix is a design decision, while the last two rows are almost always plain bugs with one correct fix. A review should therefore clear the structural rows (synchroniser, combinational logic) before debating the architectural ones (which crossings genuinely need synchronisers versus isolation).

What a review looks for per finding

  • The exact source and capture flops, and the reset net driving each: pin names are not enough, the traced nets decide.

  • Which of the five shapes the finding matches, and whether the protection claimed (if any) actually covers that shape.

  • For anything waived rather than fixed: the reason the shape is safe here, the evidence behind it, and the condition that would invalidate the waiver.

Common pitfall

Downgrading a “different reset” finding because the two resets “come from the same pin” is the most common bad waiver. The pin is not the domain: separate synchronisers and separate distribution mean separate domains.

Check yourself A finding reports combinational logic on a reset net. Is this usually waived or fixed, and how?

Fixed: remove the logic so the synchroniser output reaches the flops unmodified. There is rarely a safe reason to reshape a reset net with gates.

Check yourself Which two categories are most often genuine bugs rather than design decisions?

Missing synchroniser on the release path, and combinational logic on the reset net. Both have one standard fix and seldom admit a safe waiver.

Related topics

  • Reset ordering violations

  • Reading RDC findings

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See also

  • Reading RDC Findings