A gate is a dated decision with criteria on both sides: entry criteria say the design is ready to be judged, exit criteria say what “pass” means. CDC gates ride on the project's existing milestones so they inherit dates and authority instead of begging for both.
Gate | Entry criteria | Exit criteria |
|---|---|---|
First integration | Setup reviewed; clock and reset intent documented | Structural analysis runs cleanly on the integrated design; no setup errors remain |
Block signoff | Block RTL functionally complete; boundary models generated | No unexplained findings inside the block; boundary crossings assigned owners |
Pre-synthesis | All blocks signed off; flat run complete | No defect-class findings open; every waiver jointly approved with evidence |
Pre-tapeout | Netlist available; constraints final | Gate-level re-check clean; constraints reviewed against the final inventory; dynamic checks run |
The gate review itself is short when the paperwork is done beforehand: checklists completed, waiver evidence attached, dashboard history continuous. The meeting then handles only exceptions — disputed classifications, thin waiver evidence, scope disagreements. A gate meeting that re-derives basic facts from scratch is a sign the entry criteria were not enforced, and its approvals should be treated as provisional until the paperwork catches up.
A gate judged on an unready design produces waivers against noise: findings get waived because the design “will change anyway”, and those waivers linger into revisions where they no longer apply. Enforcing entry criteria — refusing to judge an unready design — is what keeps the waiver list honest. Postponing a gate is cheaper than laundering its findings.
The flat-versus-hierarchical rhythm from the tool-flow topic maps directly onto these gates: block signoff is hierarchical, pre-synthesis and pre-tapeout are flat. Each flat gate re-checks the boundary assumptions the hierarchical work relied on.
It violates entry criteria and manufactures waivers against noise. The gate should be postponed; judging an unready design converts unknowns into fake approvals that outlive the revision.
Block signoff is hierarchical for speed and ownership; pre-synthesis and pre-tapeout are flat to check boundary assumptions against reality. The flat gates are the proof the integration holds.