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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
    • Gray Code Crossing
    • Reconvergence Analysis
      • What Is Reconvergence
      • How It Arises
      • Why Tools Flag It
      • Removing Reconvergence
    • Multi-bit Crossing Strategies
    • Reconvergence Debug
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Reconvergence Analysis
  1. Topics
  2. CDC & RDC
  3. Reconvergence and Gray Coding
  4. Reconvergence Analysis
  5. What Is Reconvergence

Part 4 · Reconvergence and Gray Coding · All levels

What Is Reconvergence

Two or more synchronised signals from the same source domain recombining in the destination domain.

On this page

    Reconvergence is about agreement, not settling. Each synchroniser in the design does its own job: it takes one signal across and delivers a clean, settled copy a few cycles later. Reconvergence asks the next question: when two of those copies meet again in destination logic, do they still describe the same source moment? If the two paths took a different number of cycles, the answer is no for the cycles in between.

    The shape

    A source event splitting through two synchronisers into shared destination logic.
    One source event crosses through two independent synchronisers and recombines in destination logic; skew between the paths shows a mixture.

    The two paths diverge at the source register and reconverge at the first destination gate they share. Everything between those points is the skew window: sampling-edge alignment, synchroniser depth differences, and routing delay all move the two arrivals apart.

    Why independent synchronisers can disagree on timing

    • Each chain samples the source change on the first destination edge after it arrives, and the two chains can straddle a change on different edges when the change lands near the clock edge.

    • The chains may have different depths (two flops on one path, three on another), which offsets them by whole cycles structurally.

    • Downstream destination logic after one chain but not the other adds further offset before the two meet.

    • None of this is metastability: every flop involved settles correctly. The failure is a legal 0 and a legal 1 arriving in the wrong combination.

    Reconvergence is not metastability

    Metastability

    Reconvergence

    Where

    Inside one sampling flop

    At the meeting point of two settled paths

    Symptom

    Late or unpredictable resolution of one bit

    A combination of correct bits that never coexisted

    Fix direction

    More settling time (extra flop stages)

    Less independence (one crossing, derive the rest locally)

    Interview

    “Two 2FF synchronisers, both clean, yet the design fails. Why?” The expected answer: the two signals reconverge, and the synchronisers do not promise same-cycle arrival. Sketch the split above and offer the fix: synchronise one signal and derive the other in the destination domain.

    Check yourself A destination AND gate takes its two inputs from two separate synchronisers fed by the same source pulse. The pulse is long enough that neither synchroniser misses it. What can still go wrong?

    The AND can output 1 a cycle early or late relative to the intended combination, or see 10 or 01 mixtures, because the two synchronised copies arrive on different destination cycles. Lengthening the pulse fixes missing, not skew.

    Related topics

    • Next: how it arises

    • Worked example with fix

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    See also

    • Why Tools Flag It
    • Removing Reconvergence