Reconvergence Analysis

What this topic teaches

Reconvergence Analysis focuses on closing CDC/RDC risk with mechanism-level reasoning. Signals synchronized along different paths may reconverge with phase skew, creating functionally illegal combinations despite structurally legal crossings. Senior signoff depends on proving behavior with targeted evidence, not just clearing tool warnings.

The senior-engineer question

When reconvergence hazard count, false alarm ratio, silicon-escape risk index regresses, can you classify the hazard, identify accountable owners, and choose the smallest fix or waiver backed by evidence?

CDC/RDC SIGNOFF FLOW — Reconvergence Analysis

crossing inventory + reset map
          |
          v
crossing classification (level/pulse/bus/reset)
          |
          v
structure + protocol + reset checks
          |
          v
critical issues + waiver review
          |
          v
fix / validate / regress / signoff

Picture the crossing behavior

Draw the behavior before touching tools. These visuals are the expected whiteboard baseline for reviews and interviews.

Reconvergence skew

signal A --sync path 1--                             logic merge -> hazard
signal B --sync path 2--/

Individually synchronized signals can still combine illegally.

Crossing sequence

CROSSING FLOW — Reconvergence Analysis

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: reconvergence hazard count, false alarm ratio, silicon-escape risk index

Ownership layers

CDC/RDC OWNERSHIP LAYERS — Reconvergence Analysis

layer                 owns                            common failure
------------------    -----------------------------   -----------------------------
design intent         crossing architecture           wrong topology selected
protocol semantics    req/ack, fifo, ordering        liveness/deadlock bugs
reset behavior        assert/deassert sequencing      boot instability
analysis setup        tool rules + waivers            false confidence
signoff governance    risk acceptance + dashboard     stale critical waivers

Evidence to collect

• Primary metric: reconvergence hazard count, false alarm ratio, silicon-escape risk index.

• Primary artifact: reconvergence report, fanout cone map, functional hazard classification.

• Owners to involve: CDC owner, verification owner, design owner.

• At least one reproducer tied to mode/reset/traffic context.

• Decision record: fix, waive, or escalate with rationale.

Ownership map

OWNERSHIP MAP — Reconvergence Analysis

artifact                  owner
----------------------    -------------------------
design intent           CDC owner
verification evidence   verification owner
signoff decision        design owner

Every open CDC/RDC issue needs one accountable owner before waiver or fix.

Subpages in this topic

Each topic includes mechanism, I/O contract, metrics, debug, worked example, pitfalls, interview drills, checklist, theory, design tradeoffs, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• Classify crossing/reset hazards before proposing fixes.

• Pair structural results with protocol/reset behavioral proof.

• Treat waivers as bounded risk contracts, not cleanup shortcuts.

Common pitfalls

• Mass-waiving warnings near tapeout.

• Assuming local IP cleanliness guarantees SoC behavior.

• Skipping reconvergence and reset stress after CDC fixes.

CDC/RDC deep dive

Reconvergence failures are timing + logic coupling hazards.

Concept diagram

RECONVERGENCE

branch A sync --                 -> merge logic -> illegal combination window
branch B sync --/

Metric graph

HAZARD REPRODUCTION RATE

before fix: 1/2000 runs
after fix: 0/100000 runs

Reports and artifacts

• reconvergence warnings

• gray transition checks

• hazard replay traces

• multi-bit strategy map

Mini case study

Gray pointer was legal, but downstream merge decoded mixed-era values during burst stress.

Debug branches

• Trace fanin cones

• align event windows

• verify decode assumptions

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.