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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
    • Gray Code Crossing
      • The One-Bit-Change Rule
      • Gray Counters
      • Where Gray Fails
      • Non-Power-of-Two Depths
    • Reconvergence Analysis
    • Multi-bit Crossing Strategies
    • Reconvergence Debug
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Gray Code Crossing
  1. Topics
  2. CDC & RDC
  3. Reconvergence and Gray Coding
  4. Gray Code Crossing
  5. Non-Power-of-Two Depths

Part 4 · Reconvergence and Gray Coding · All levels

Non-Power-of-Two Depths

Why a Gray pointer ring must be an even-length cycle, and the limits for other depths stated plainly.

On this page

    The one-bit promise has to hold on every step, including the step from the last value back to zero. That wrap step is where non-power-of-two depths fail, and the reason is parity, not tooling.

    A Gray ring must be a cycle of even length

    Each step flips one bit, which flips the parity of the popcount. Returning to the starting value needs the starting parity back, so any single-bit-change cycle has an even number of steps. An odd depth can never visit each entry exactly once with single-bit steps and a single-bit wrap. The n-bit binary-reflected Gray code gives the full 2^n cycle, wrap included: 3-bit Gray ends ...011, 010, 110, 100 and returns to 000 with one bit.

    Truncation does not wrap (illustrative check)

    Take a 4-bit counter truncated to depth 10, values 0 to 9. The wrap step goes from 9 to 0:

    Diagram
    illustrative check of the wrap step for a depth-10 truncation
    Gray(9): binary 1001, Gray = 1001 ^ 0100 = 1101
    Gray(0): 0000
    bits differing between 1101 and 0000: 3
    result: the wrap step flips three bits, so the ring is not Gray

    Depths 12 and 14 fail the same way with their own wrap steps. There is no standard combinational formula that produces a cyclic Gray order for an arbitrary depth, so do not invent one.

    What to do instead

    Situation

    Standard approach

    Free choice of depth

    Use a power of two. This is the normal answer for Gray-pointer FIFOs (see async FIFO design).

    Depth fixed at a non-power of two

    Keep a power-of-two Gray ring at or above the depth and size full and empty from occupancy against the real depth, or move the transfer to a handshake.

    Odd depth

    A single-bit-change cycle visiting each entry once is impossible by the parity argument above; use a handshake or FIFO of a neighbouring depth.

    Custom even-length sequence

    Allowed only with an exhaustive adjacency proof covering the wrap, exactly like the Gray counter check. State plainly that the sequence is custom and keep the proof with the design.

    Common pitfall

    Rounding the depth up to a power of two wastes entries but keeps the standard full and empty comparison. Shrinking the ring to the exact depth keeps the entries but needs custom full and empty logic plus a custom proof. Reviewers should confirm the team picked one of these deliberately, not truncated and hoped.

    An even depth does not rescue truncation either. Depth 12 fails on its own wrap step (Gray of 11 against Gray of 0), and only a constructed even-length cycle with a proven wrap, checked exactly like the counter in the previous lesson, is acceptable. When a design claims one, ask for the proof first and the depth justification second.

    Check yourself A specification fixes a FIFO depth of 12. The designer truncates a 4-bit Gray counter to 0..11. What is wrong, and what are the two standard fixes?

    The wrap step from 11 to 0 flips more than one bit, so pointer samples near the wrap can tear. Fix one: run a 16-deep Gray ring and assert full at occupancy 12. Fix two: carry the data by handshake instead of Gray pointers.

    Check yourself Why is an odd FIFO depth, say 9, impossible for a Gray pointer ring rather than just inconvenient?

    Each Gray step flips parity, so returning to the starting value needs an even number of steps. Nine entries can never form a single-bit-change cycle that visits each entry once and wraps cleanly.

    Related topics

    • Where Gray fails

    • Alternative: mux recirculation

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    See also

    • The One-Bit-Change Rule
    • Gray Counters