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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
    • Gray Code Crossing
    • Reconvergence Analysis
      • What Is Reconvergence
      • How It Arises
      • Why Tools Flag It
      • Removing Reconvergence
    • Multi-bit Crossing Strategies
    • Reconvergence Debug
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Reconvergence Analysis
  1. Topics
  2. CDC & RDC
  3. Reconvergence and Gray Coding
  4. Reconvergence Analysis
  5. How It Arises

Part 4 · Reconvergence and Gray Coding · All levels

How It Arises

Typical causes of reconvergence with a pattern table and a simulated glitch waveform.

On this page

    Reconvergence is rarely drawn deliberately. It grows when two signals that belong together are given two independent crossings because each looked like a single-bit problem on its own. The destination then combines clean copies that describe different source moments.

    Typical causes

    Pattern

    What crosses separately

    What the destination sees

    Related control bits

    Two enables from the same state machine, each with its own synchroniser

    One enable applied a cycle before the other

    Pulse plus qualifier

    A strobe and the valid bit that says what it means

    The strobe fires with a stale qualifier, acting on old meaning

    Derived enables

    An enable synchronised directly, plus the same enable recomputed from another synchronised signal

    The two copies disagree for the skew window

    Status consumed together

    Two status flags sampled as a pair (for example empty plus error)

    A flag pair that never coexisted drives the decision

    Data plus its own valid

    A quasi-static bus sampled freely alongside a synchronised valid

    New data with old valid, or old data sampled as new

    Simulation: the glitch

    The waveform below is simulation output for a source strobe req_s and its qualifier qual_s rising together, each crossing through its own synchroniser into the destination domain. The qualifier path carries one extra destination flop standing in for one cycle of skew between the two synchroniser paths. bad is req_d & ~qual_d: the inconsistent combination.

    How to read it: one slot is one source-clock cycle. req_s and qual_s rise together and are both high from slot 2.

    • req_d rises in slot 5, two destination edges after the change; qual_d follows one destination cycle later in slot 7.

    • bad is high across slots 5 and 6: the destination sees the request without its qualifier for one full destination cycle.

    • The release is clean: both sources fall together in slot 10, req_d falls in slot 13 and qual_d in slot 15, and bad stays low throughout because the request drops first.

    • Every flop settles correctly throughout. The glitch is skew between two correct paths, not metastability.

    Common pitfall

    The fall is clean in this waveform by construction, not by principle. With the skew on the other path, or with a qualifier that drops before the strobe, the release edge glitches instead. Analyse both edges of every related pair.

    Check yourself The two synchronisers in the waveform have depths two and three. Where does the one-cycle offset in the destination come from?

    Structurally, from the extra flop on the qualifier path, which stands in for sampling or routing skew between the paths. req_d settles two destination edges after the change and qual_d three after, so they disagree for one cycle.

    Related topics

    • What is reconvergence

    • Next: why tools flag it

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    See also

    • Removing Reconvergence
    clk_sreq_squal_sclk_dreq_dqual_dbad
    Simulation output: separately synchronised request and qualifier arriving a cycle apart, so the destination briefly sees the request without its qualifier