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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
    • Crossings and Failure Modes
      • What Is a Crossing?
      • Domain Relationships
      • Failure Modes
      • Why Simulation Misses CDC
    • Identifying Domains
  • Metastability and Synchronizers16
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Crossings and Failure Modes
  1. Topics
  2. CDC & RDC
  3. Clock Domains and Failure Modes
  4. Crossings and Failure Modes
  5. Domain Relationships

Part 1 · Clock Domains and Failure Modes · All levels

Domain Relationships

Synchronous, related, mesochronous, plesiochronous and asynchronous clock pairs, and why the relationship decides the method.

On this page

    Not all crossings are equally hard. The relationship between the two clocks decides how much you know about the arrival phase, and that decides which synchronisation method is safe.

    The five relationships

    Relationship

    What the clocks do

    Example

    Synchronous

    One clock net; fixed phase by construction

    Two flops on clk_a in different blocks

    Related (same source, fixed ratio)

    Different nets from one source with a fixed frequency ratio and phase

    clk and its divide-by-2 from the same generator

    Mesochronous

    Same frequency, but the phase offset is fixed and unknown

    One source split through different buffers, or a phase-shifted copy

    Plesiochronous

    Same nominal frequency, but the sources are independent so the phase drifts slowly through every value

    Two boards each with their own oscillator at the same nominal rate

    Asynchronous

    No fixed frequency or phase relationship at all

    A processor clock and an independent peripheral clock

    Mesochronous and plesiochronous sound alike and fail differently. Mesochronous phase is unknown but fixed: once you have covered the worst offset, the behaviour repeats every cycle. Plesiochronous phase drifts: over minutes or hours the two edges slide through alignment, near-alignment, and every gap, so the design meets every skew it will ever see in the field, including the worst one.

    Why the relationship decides the method

    Relationship

    What you know

    What that allows

    Synchronous

    Phase everywhere

    Ordinary timing analysis; no synchroniser needed

    Related, fixed ratio

    Exact ratio and usually phase

    A synchronisation scheme chosen for the ratio and direction; the known phase can simplify the analysis but the path is still a crossing

    Mesochronous

    Phase offset, but not its value

    A scheme that tolerates any fixed offset, such as a two-flop synchroniser on a slow-changing signal

    Plesiochronous or asynchronous

    Nothing about phase

    A scheme that tolerates any phase on every transfer: synchronised levels, pulse synchronisers, handshakes, or FIFOs, with correct fast-to-slow and slow-to-fast behaviour

    Direction matters as much as the relationship. A slow event crossing into a fast domain is sampled many times, so the danger is counting it twice; a fast event crossing into a slow domain may fall between two sampling edges, so the danger is missing it. The failure modes lesson shows both.

    What the checking tools look for

    A structural analysis generally groups crossings by clock pair and asks for the relationship of each pair as part of the setup: that relationship table is checked against the synchronisation scheme found on each path. A pair declared "related" but implemented with a scheme that assumes a synchronous phase is exactly the kind of mismatch review is meant to catch.

    Common pitfall

    Treating a plesiochronous pair as mesochronous because "both are 100 MHz". The drift means the design will eventually see coincident edges; any scheme that relies on a minimum phase gap between the clocks will eventually see it violated.

    Check yourself clk_b is a divide-by-4 of clk_a from the same generator, with a known phase. Is a path from clk_a to clk_b a crossing, and does the known ratio remove the need for care?

    It is still a crossing (different nets), and it still needs a deliberate scheme: the ratio lets you pick the right one (for example, reasoning about how many fast cycles a slow sample spans), but "known ratio" alone synchronises nothing.

    Check yourself Two chips each run at a nominal 50 MHz from their own crystals and exchange data. Which relationship is that, and what does it rule out?

    Plesiochronous: the phase drifts. It rules out any scheme that needs a guaranteed minimum spacing between the two clocks' edges, since every spacing occurs eventually.

    Related topics

    • Next: Failure Modes

    • What Is a Crossing?

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    See also

    • Why Simulation Misses CDC