Real designs rarely clock every flop from a root oscillator. Dividers, gates, and muxes create the clocks the flops actually see, and each one forces the question: same domain, or a new one?
Generator | What it produces | Domain verdict |
|---|---|---|
Divider (counter or toggle flop) | A slower clock net with a fixed ratio to its source | A new domain: different net, so every path to and from the source net is a crossing, even though the ratio is exact |
Gate (integrated clock gate holding the clock off while idle) | The same frequency when running, on a different net, with missing pulses | A new domain for intent purposes: the gated flops can miss events the source domain assumes were sampled, and an enable from another domain is itself a crossing |
Mux (select between two clocks, e.g. functional versus test) | One net that carries different clocks at different times | Both source clocks are domains of every flop downstream, plus the select is a crossing into each source's timing |
The verdict above is the default, and intent can merge nets back only with evidence: a gated clock whose tree is balanced with its source and whose enable timing is closed may be treated as one domain for timing, and a divider output with a known phase may get ratio-aware treatment. The merge is a documented decision with constraints behind it, never a hallway assumption. When in doubt, keep the domains separate: an extra crossing in the list costs a review line, while a missing one costs a respin risk.
A structural analysis generally flags generated clocks explicitly: undeclared divider outputs, gated nets without an identified gate cell, and muxes on clock paths. It also looks at the gate enable and the mux select as signals in their own right: an enable arriving from another domain unsynchronised, or a select that can change while either clock runs, is reported against the generator, not just against the data crossings downstream.
How a gate must be built (latch-based cells, enable timing, test enable) is RTL design material: see clock gating. This lesson only decides what the gate means for the domain list.
No. Different nets mean a crossing, and the synchroniser is the approved scheme for a slow-changing control signal here. The known ratio simplifies the review (pulse widths and hold times can be reasoned about exactly); it does not remove the need for a scheme.
Two, depending on the mode: every flop-to-flop path through the mux must be reviewed against both clocks, and the select itself is a crossing. The test-mode crossings are real and need the same treatment as the mission-mode ones.