Most missed crossings are not exotic: they involve a clock the team forgot to list, often a slow test clock, a debug clock, or a divided clock buried three levels down. The inventory is the cheapest CDC activity there is, and it catches the most embarrassing bugs.
Start at the chip boundary and work inward. Every oscillator pin, every recovered clock (from a serial link, for example), and every test and debug clock (scan, JTAG) is a source. Then follow each source through its generators: frequency synthesisers, dividers, muxes, and gates each produce a new clock net. The lesson on generated, gated and muxed clocks decides which of those nets are new domains; here, list every net first and classify later.
Two flops on the same clock but under different resets do not behave as one domain during reset: one side can be held in reset while the other runs, so every crossing between them sees a launch or capture flop frozen at its reset value. Reset behaviour therefore belongs in the domain definition. For each clock, record each reset that acts on its flops: whether it is asynchronous or synchronous, which flops it reaches, and (for release ordering) which domain's reset comes off first. The reset synchroniser itself is design material in reset strategies; here the point is only that the inventory lists it.
Record per domain | Example entry | Why signoff needs it |
|---|---|---|
Clock net and source | periph_clk, divided from sys_pll | Defines the domain; feeds the crossing list |
Frequency or period range | 25 MHz, always on | Chooses pulse-versus-handshake schemes; spots fast-to-slow hazards |
Reset(s), type, reach | periph_rst_n, asynchronous assert, all periph_clk flops | Release behaviour changes what the crossing sees at power-up |
Special modes | Scan shifts on tck; debug halts periph_clk | Test clocks create crossings the functional design never sees |
A structural analysis generally starts from the declared clocks and resets and then reports anything it finds that was not declared: an undriven clock pin on a flop, a generated net with no declared source, a reset with no declared domain. Treat every such report as an inventory gap first and a design bug second: update the list, then judge the circuit.
Functionally yes, but during the reset sequence it is not: P's flops sit at reset values while Q's run. The crossing needs reset-aware review (what Q sends before P is awake, and what P's reset values do to Q's inputs), which is why the domain entry includes the reset.
Yes. It is a clock net driving flops, so paths to and from it are crossings whether or not the hierarchy hides them. "Inside the IP" is where forgotten clocks live.