The two-flop synchroniser carries a level, not an event. Whether a signal may cross directly depends on how long it holds still compared with the destination clock.
A level must stay stable for at least two destination clock periods so that, wherever the sampling edges land, the destination sees the value at least once and the synchroniser has time to deliver it. In practice designers hold source levels longer still, and the exact margin belongs to the project's CDC policy.
Signal | Crossing treatment |
|---|---|
Level stable for many destination periods (enable, state, status) | Direct two-flop synchroniser. |
Level stable for just about two destination periods | Direct crossing at the limit; confirm the margin with the slower clock's worst case. |
Pulse one source cycle wide, or any event shorter than the destination period | Must not cross directly; use a pulse scheme. |
A pulse shorter than the destination period can rise and fall entirely between two sampling edges and vanish: the destination never sees it. Stretching the pulse in the source domain past two destination periods turns it into a level, and where the clocks are unrelated the robust answer is a toggle scheme or a handshake, covered by the pulse synchroniser topic of this course.
The RTL course shows the baseline circuit and a lost-pulse simulation in Metastability and Synchronisation; read that lesson for the design view and keep this course's signoff view alongside it.
No: the 25 MHz period is 40 ns, so 60 ns is only 1.5 destination periods, less than the two-period hold rule. A change can be missed or sampled just once with no margin. Hold the flag for more than two destination periods (plus project margin) or use a handshake.
Because a hold of more than two destination periods guarantees at least one clean sample regardless of phase: some sampling edge falls far enough from both transitions of the level for the first flop to capture a stable value, which the synchroniser then delivers.