Parts 11 and 12 taught how to find and contain coherence bugs. A staff engineer is also asked when: which risks to spend the remaining weeks on, what to do with a race found three weeks before tape-out, how to run a hang that nobody can explain, and what evidence must exist before anyone signs. This topic turns the course's verification and debug methods into those program decisions. Every program, date and number here is illustrative.
Lesson | After it you can... |
|---|---|
List the coherence risks of a chip program with indicator, mitigation and owner, and rank them by likelihood, impact and detectability. | |
Choose between an RTL fix, a chicken bit, a software workaround and an erratum, and defend the choice with stated criteria. | |
Run a rare pre-tape-out hang with a triage plan, single owners, daily status and a decision deadline. | |
Write the coherence tape-out checklist, say who signs each item and reject evidence that is out of date. |
Suggested order: the four lessons in sequence. They assume Closure Evidence from Part 11 and the chicken bit and hang triage lessons from Part 12.
Evidence. A listed test is a plan, not a result. Each risk needs an early indicator that is measured (a coverage bin, a failure rate, a proof status) and a date by which it must move. A risk is retired by what the indicator shows, not by the existence of a plan.