Often it can be avoided, not fixed. A chicken bit is a configuration field that switches off one optimisation and sends the controller down a simpler, slower path that does the same job. If the bug lives only in the optimised path, setting the bit makes it unreachable. The fix still needs a new stepping; the bit keeps the current parts shippable until then.
The rule: a chicken bit selects between two behaviours that both exist in the RTL and were both verified. It never creates a new path. In hardware it is a field in a configuration register that the controller's decision logic reads, as one more input to the choice. In H's request decoder, for example, a dirty-holder GetM chooses between sending a Fwd-GetM that asks the holder for direct Data to the requester, and one that asks for Data back to H.
Property | Why |
|---|---|
Programmed by boot firmware before coherent traffic starts, then locked | Changing the route while a transaction is pending can strand it: H expects Data at H that was sent to C1. |
Every controller that depends on it sees the same value | If H uses four-hop but a cache assumes direct transfer, they disagree about where the Data goes. |
Readable, and visible in counters | Proves the bit took effect: with direct transfer disabled, the direct-transfer counter must read zero. |
Its fallback path is in the pre-silicon regression | Otherwise the workaround is an untested second protocol. |
Take the Three-Hop Versus Four-Hop traces as they stand: C0 M / 1, C1 wants to write, H exclusive(C0), memory = 0. With the bit clear, H runs the three-leg route there. With the bit set, the same GetM runs the four-leg route of the same lesson. The table compares them without redrawing either trace.
Bit | Route | Legs on C1's critical path | Data passes through H | Final state |
|---|---|---|---|---|
Clear | Fwd-GetM, C0 sends Data to C1 | 3 | No | C0 I / -, C1 M / 1, exclusive(C1), memory = 0 |
Set | Fwd-GetM, C0 sends Data to H, H sends Data to C1 | 4 | Yes | C0 I / -, C1 M / 1, exclusive(C1), memory = 0 |
The end state is identical; only the latency and H's buffer use change. That is the test of a good workaround: values and final states do not depend on the bit, only cost does. Any race that exists only because Data bypasses H, such as the one in An Illustrative Escape, where the four-hop Data tells H the coming PutM is stale, disappears.
Illustrative bug | Workaround bit | Cost |
|---|---|---|
A race exists only when Data goes straight from holder to requester | Disable direct transfer: H buffers Data (four-hop) | One extra leg on every dirty-miss critical path, more traffic and buffer occupancy at H. |
A race in the E path, for example PutE crossing a forward | Never grant E: a lone reader gets S, as in MSI, so no silent E to M can happen | Read-then-write private data needs an upgrade GetM (SM^D) after the first read. |
Dirty writeback corrupts lines of one address region | Force write-through for that region: lines never become dirty | Every store writes memory: bandwidth and power on that region. |
Two concurrent upgrades in one H bank lose an Inv | Serialize the request class: one outstanding upgrade per bank | Lower throughput when many cores contend for lines in that bank. |
A snoop-filter eviction races with a request | Disable the filter and broadcast snoops | Snoop bandwidth grows with the number of caches. |
Costs are workload-dependent: measure them with the regression's performance tests before and after, on the workloads customers run, and publish the bit and its cost in the errata.
Set the bit, then rerun the whole coherence regression, not just the test that failed: the fallback path now carries all traffic and may hit its own bugs. Confirm with counters that the optimisation is really off. Confirm the original failure no longer reproduces at the original rate and seeds. Pre-silicon, each bit should have had its own random regression with the bit set; a bit only ever exercised by a smoke test is a hope, not a workaround.
A full coherence regression with the bit set, in simulation or emulation and on silicon. The fallback is now the main path and has had no stress. The workaround can carry its own bug, and it must be found before customers run on it.