Pre-silicon verification explores a model for minutes of simulated time. Silicon runs billions of transactions per second with delays nobody modelled. This topic covers what a coherence team runs on the first chips, how a bug found there is contained with a configuration bit while the fix waits for the next stepping, and how the tests that found it become a permanent guardrail.
Lesson | After it you can... |
|---|---|
Run SB, MP, IRIW and CoRR many times, and read a forbidden outcome as a bug and a missing allowed one as no evidence. | |
Choose a workaround bit, state its cost, and explain why its fallback path must already be verified. | |
List what a post-silicon coherence regression contains and how its failures are bucketed and gated. | |
Walk one escaped race from first symptom to workaround, fix and new pre-silicon coverage. |
Read in order. It assumes the SB and MP enumerator and the triage topic of this Part.
No. A run samples timings; it does not enumerate them. The forbidden outcome may need a delay the harness never created. Only a forbidden outcome observed is conclusive (it is a bug); its absence is evidence of the strength of the stress, not proof.