On silicon a coherence bug cannot be rerun with full waveforms. You get one failure, a trace buffer of limited depth and whatever state you can dump. This topic teaches the coherence-specific evidence: which messages to capture, how to rebuild transactions from them, and how to go from a stale read or a hang to the first illegal step. The general method (observe, hypothesise, test) belongs to the Hardware Debug course; here we apply it to coherence.
Lesson | After it you can... |
|---|---|
Name the minimal per-message record and rebuild a dirty read from a capture. | |
Find who supplied an old value and replay a log to the first illegal step. | |
Build a wait-for chain from pending entries and MSHRs and tell a lost message from a cycle. | |
Go from an observed symptom to likely mechanisms and the first evidence to collect. |
Suggested order: as listed. Prerequisites: the race lessons, controller resources and progress classes. Every example uses the course model with MSI and acknowledgements collected at H.
The load is the symptom. The first illegal step is usually earlier: a grant sent before an Inv-Ack, an Inv never sent, or memory answering while a cache held dirty data. The captured messages for X's line, in H's order, locate that step.