Part 11 answers: What do we do when the chip comes back?
First silicon runs at full speed with real software and real electrical conditions, and almost no visibility. Bugs that escaped every pre-silicon technique appear here, along with failures that depend on voltage, temperature and process.
This part covers what changes after tape-out, planning validation before silicon returns, observability in silicon, debugging with almost no visibility, margins and characterisation, deciding between fix, workaround and documentation, and turning every escape into a lasting improvement.
Plan silicon validation and its observability before tape-out.
Debug a silicon failure from symptom to root cause.
Decide between a respin, a workaround and an erratum.
Answer each in your head before opening it. If two or more feel shaky, revisit Part 10: Emulation and Prototyping first.
Booting needs billions of cycles; an emulator runs them in about an hour where simulation would take about two months.
Fidelity (different clocks, memories, timing) and much of the debug visibility, for speed.
Capture state and trace around the failure with triggers, then reproduce a short window in simulation.
# | Lesson | Level | Status |
|---|---|---|---|
11.1 | W · Working | Ready | |
11.2 | S · Senior | Ready | |
11.3 | S · Senior | Ready | |
11.4 | S · Senior | Ready | |
11.5 | S · Senior | Ready | |
11.6 | P · Principal | Ready | |
11.7 | P · Principal | Ready | |
— | all levels | Ready |
Every lesson in this part is ready. Work through them in order: each one sets up the problem the next one solves.
This course teaches the decisions behind verification. These lessons teach the tools and syntax that carry them out, so this part links to them instead of repeating them.