Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
Every pre-silicon method has limits: functional corners, scale, integration, electrical effects and specification mistakes remain.
Debug features in the design, ready test programs, lab infrastructure, and a silicon plan from pre-silicon gaps.
Through designed-in observability: status and counters, trace buffers with triggers, scan dumps, reached through a debug port.
Capture before reset, reproduce reliably, separate functional from electrical, localise, capture the window, reproduce in RTL.
Treat it as electrical: shmoo across voltage, temperature and frequency, correlate with timing analysis, then guard-band, screen or fix.
On impact, exposure, workaround quality and fix cost; hardware fixes for silent corruption and security, workarounds when complete, errata for rare low-impact cases.
Classify the gap, add a test and the missing check or coverage, sweep for the class, change the plan and process.
Task. First silicon of a network SoC arrives Monday. Over the first month, sketch: the bring-up order for the first day, how you would triage the first three failures (a boot hang, packet loss only above 100 °C, wrong values in a statistics register), and what each failure should change in the verification process.
Day one: power and clocks, reset, debug port access, read ID and reset-value registers, run the first bare-metal program from boot flash, then one packet through each port, then the boot flow. Boot hang: capture state before reset (status, program counter, scan dump if frozen); reproduce; vary voltage, temperature and clock (a hang that doesn't move is functional); localise with trace triggers on the last interface active; replay in RTL or emulation. Packet loss above 100 °C: electrical; shmoo it across parts, compare the boundary with the specified temperature range, correlate with static timing analysis, choose guard band, screen or metal fix. Statistics register: functional and probably cheap; compare with the register specification; likely a software workaround plus erratum. Process changes: for the hang, the missing check or scenario added to the plan and a sweep for the class; for the hot failure, timing constraints and margins reviewed for that path type; for the register, a register app or read-back test added to the standard checklist.
Speed becomes unlimited, visibility nearly disappears, and fixes jump from minutes to weeks or months.
F25, F26 and F28: pre-silicon left them without evidence or only partial evidence.
IEEE 1149.1 (JTAG).
Every flip-flop's value at one moment; it requires stopping the clock and reuses test scan chains.
The frozen state is the best evidence and disappears at reset.
It failed identically across voltage, temperature and clock speed.
Above about 80 °C.
It protects only software that applies it in every path; one missed path corrupts data silently.
Unreached, masked, unchecked, unspecified.
Bugs come in classes; the same misunderstanding usually appears elsewhere.