Lesson 3.2 noted that DCRouter's credit counters are invisible at its pins, so a lost credit shows only as lower throughput. In simulation that was an inconvenience; a credit audit made it visible. In silicon, after hours of traffic, an output that has slowed to a crawl is exactly that symptom, and no audit can be run on the testbench's terms. Whether the cause can be seen depends entirely on what the designers put in the chip.
How do you see inside a chip?
The obvious hope is to probe the chip like a board, or to rely on the external interfaces. Internal signals are not reachable by probes, and external behaviour is usually far removed from the cause, both in place and in time. What can be seen inside silicon is decided at design time, by the observability features built in.
Mechanism | Shows | Cost | Limit |
|---|---|---|---|
Status registers | Current state summaries (locks, sleep, modes) | Tiny | Only what was chosen; only the present |
Event and performance counters | How often things happened (errors, packets, stalls) | Small | Counts, not order or timing |
Trace buffers | A recorded window of selected signals or transactions around a trigger | Medium (memory) | Short window, few signals, chosen in advance |
Scan dumps | Every flip-flop's value at one moment, read out through the scan chains | Reuses test scan; the chip stops | One snapshot, and the clock must be stopped |
Trigger logic | When to capture: an event, a counter value, a synthesised assertion | Small | Triggers must be designed or programmable |
Debug access usually rides on a standard test port such as JTAG (fact V13), which also reaches the scan chains used for manufacturing test.
Symptom | What would show the cause |
|---|---|
An output slows to a crawl | Credit counts in STATUS (if added, lesson 3.6); a trace of out_vld and out_crd |
Traffic stops on one input | STATUS sleep and lock bits; PKT_CNT; a trace triggered on in_vld held high with in_rdy low for 1,000 cycles |
Packets arrive with out_err unexpectedly | ERR_CNT per input; a trace of headers and tails at that output |
Everything stops | A scan dump: FIFO pointers, locks, owners and credits all at once |
Status for hidden state: credits, occupancy, state machines (lesson 3.6).
Counters for rates: errors, packets, stalls, retries.
Trace on key interfaces: transaction-level where possible, so the window holds more history.
Programmable triggers: including synthesised versions of key assertions (lesson 10.6).
Scan dump support: a way to stop clocks cleanly and read the state.
Practice | Purpose |
|---|---|
On-chip debug and trace infrastructure on every major interface | Windows of history around failures |
Performance monitoring units | Counts and rates for performance and anomaly detection |
Scan-dump flows linked to the RTL's flip-flop names | A frozen state readable as RTL signals |
Lesson 11.2's cache-controller story is the typical cost of missing observability: six weeks of experiments for a cause a small trace buffer would have shown in an afternoon. The opposite failure is real too: trace buffers placed on interfaces where nothing ever goes wrong, and none on the new, risky block. Observability should follow the risk ranking (lesson 9.3).
A hang is a frozen state worth one snapshot; a slow-down is a history of events, which needs counters or a trace over time.
The credit counts: lost credits show only as reduced throughput, and simulation needed a credit audit to see them.
In silicon you see only what was designed to be visible.
Status and counters summarise; trace buffers record windows; scan dumps snapshot everything.
Place observability by risk, and give hidden state status registers.