A failure report from the lab: the SoC drops packets, but only in the temperature chamber above 85 °C, and only on some boards. At room temperature, every board passes every test for days. Nothing about DCRouter's logic depends on temperature. Something about its timing does.
A failure appears only when hot. Now what?
The obvious response is to look for a logic bug in the failing feature. A functional bug fails the same way at any voltage, temperature or clock speed, because logic does not change with conditions. A failure that appears and disappears with conditions is electrical: a path too slow, a supply drooping, a signal disturbed. Debugging it as logic wastes weeks; characterising it finds where the margin ran out.
Condition | Effect on a digital chip | Failure that moves with it |
|---|---|---|
Supply voltage | Lower voltage makes transistors slower | Setup-time failures at low voltage |
Temperature | In many processes, hotter means slower logic | Failures only when hot |
Clock frequency | Shorter period leaves less time per cycle | Failures above a frequency |
Process variation (the individual part) | Some parts are faster, some slower | Failures on some boards only |
A shmoo plot sweeps two conditions and marks pass or fail at each point; its boundary shows the operating region and the margin to the specified corner.
An illustrative critical path whose delay grows with temperature and as voltage drops, in a chip clocked at 1 GHz. The model prints the shmoo and the minimum passing voltage at each temperature.
"""Margins: a failure that moves with voltage and temperature.
One critical path on a chip (illustrative): its delay is 0.88 ns at 1.0 V and 25 C, grows by
0.25% per degree C, and grows as the supply drops, by (1.0 / V)^1.6. The chip runs at 1 GHz,
so the path must finish within 1.0 ns. The model prints a shmoo plot (pass or fail at each
voltage and temperature) and the minimum passing voltage at each temperature.
"""
temps = [-40, 0, 25, 50, 85, 105, 125]
volts = [0.80, 0.85, 0.90, 0.95, 1.00, 1.05]
def delay(v, t):
return 0.88 * (1 + 0.0025 * (t - 25)) * (1.0 / v) ** 1.6
print(" V \\ T " + "".join(f"{t:>6d}" for t in temps))
for v in reversed(volts):
print(f" {v:.2f} " + "".join(f"{' pass' if delay(v, t) <= 1.0 else ' .'}" for t in temps))
vmin = []
for t in temps:
ok = [v for v in volts if delay(v, t) <= 1.0]
vmin.append(min(ok) if ok else None)
print("min passing V: " + " ".join(" none" if v is None else f"{v:6.2f}" for v in vmin))
assert vmin[0] is not None and (vmin[-1] is None or vmin[-1] > vmin[0])
print("PASS: the same path passes at 0.85 V when cold and needs more voltage as it heats, failing at 1.0 V above about 80 C")It prints:
V \ T -40 0 25 50 85 105 125
1.05 pass pass pass pass pass pass .
1.00 pass pass pass pass . . .
0.95 pass pass pass . . . .
0.90 pass pass . . . . .
0.85 pass . . . . . .
0.80 . . . . . . .
min passing V: 0.85 0.90 0.95 1.00 1.05 1.05 none
PASS: the same path passes at 0.85 V when cold and needs more voltage as it heats, failing at 1.0 V above about 80 CHow to read it: at the nominal 1.0 V the path passes up to 50 °C and fails at 85 °C (the boundary is near 80 °C). Cold, it passes even at 0.85 V. The failure moves smoothly with both conditions, which is the signature of a timing margin, exactly the opening report. A part with slower transistors would shift the whole boundary, which is why only some boards fail.
Shmoo it across voltage, temperature and frequency, on several parts, to map the boundary.
Compare with the specification's corners: if the failure is inside the specified operating range, it is a real problem; outside, it is margin information.
Find the path: correlate with static timing analysis and with which feature fails.
Choose a response: raise voltage or lower frequency for affected parts, screen parts in production, fix the path in a metal change or respin (lesson 11.6).
Practice | Purpose |
|---|---|
Shmoo plots for every major interface and frequency | Operating region and margin mapped |
Characterisation across many parts and process corners | Part-to-part variation understood |
Correlation with static timing analysis | Failing paths identified and fixes targeted |
Production test limits set from characterisation | Weak parts screened before shipping |
A team (illustrative) spent two weeks reviewing the RTL of a block that failed only in the hot chamber, looking for a logic bug. A shmoo on the first day would have shown the failure moving smoothly with voltage and temperature, pointing at a timing path, which static timing analysis then identified as an under-constrained path crossing two clock domains.
Individual parts differ in transistor speed; slower parts have less timing margin, so their pass boundary is closer to the operating conditions.
1.05 V: at nominal 1.0 V the path fails at 85 °C, so the chip has no margin there unless voltage is raised or frequency lowered.
Electrical failures move with voltage, temperature, frequency and the part; functional bugs do not.
Shmoo plots map where a chip stops working and how much margin it has.
Classify early, then correlate with timing analysis and choose a guard band, a screen or a fix.