Term | Meaning |
|---|---|
Assertion | A rule checked automatically while the design runs, at the place it applies |
Bug escape | A bug that passes every check and is found later, in silicon or in the field |
Closure | Reaching the coverage and other criteria the plan set as done |
Constrained random | Random stimulus limited to legal values by constraints that model the environment |
Controllability | How easily a test can put the design into a given state |
Coverage | A measure of which situations the tests exercised (not whether results were checked) |
Directed test | A test written by hand for one specific case |
Emulation | Running the design on special hardware, far faster than simulation, with some debug visibility |
False pass | A test that passes without having checked anything, such as a vacuous assertion |
Formal verification | Checking a property against every input sequence the assumptions allow, by proof |
Mutation testing | Injecting deliberate bugs to measure whether the testbench catches them |
Observability | How easily a wrong internal value becomes visible to a check |
Oracle | Whatever decides what the correct result is: a model, a table, a rule or a person |
Reference model | A model that computes the expected output for any input |
Regression | The set of tests run repeatedly to catch new failures |
Residual risk | The risk of remaining bugs that a sign-off decision accepts |
Scoreboard | A checker that compares the design's outputs with expected outputs |
Sign-off | The decision that verification is complete enough to proceed, on stated evidence |
Validation | Checking that the product meets the real need, not only its specification |
Verification plan | The document that lists features, checks, coverage, priorities and owners |
Waiver | A recorded, approved exception to a sign-off criterion |