Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Paths
  • Concept Map
  • Meet DCRouter
  • Glossary
  • Part 0: What Verification Is8
    • Verification, Validation and Test
    • The Cost of an Escape
    • Intent, Design and Implementation
    • You Cannot Test Everything
    • Confidence, Not Proof
    • The Verification Stack
    • Meet DCRouter
    • Drills: What Verification Is
  • Part 1: What Can Go Wrong11
  • Part 2: Specifications as Checkable Rules8
  • Part 3: Observability and Controllability7
  • Part 4: Stimulus11
  • Part 5: Checking11
  • Part 6: Coverage10
  • Part 7: Formal and Simulation10
  • Part 8: Verification Levels and Reuse8
  • Part 9: Planning and Risk9
  • Part 10: Emulation and Prototyping8
  • Part 11: Post-Silicon Validation8
  • Part 12: Bug Economics8
  • Part 13: Debug7
  • Part 14: Sign-Off7
  • Part 15: Verification in Context8
  • Part 16: Case Studies5
  • Part 17: Capstones5
  • Part 18: Interview Preparation6
Loading lesson

‹First Principles of Verification Strategy
  1. Topics
  2. First Principles of Verification Strategy
  3. Part 0: What Verification Is

Part 0 · What Verification Is · All levels

Part 0: What Verification Is

What does it mean for a chip to work? Explain the difference between verification, validation and manufacturing test.

  • 8topics
  • 8lessons
On this page

    Part 0 answers: What does it mean for a chip to work?

    Where Part 0 sits among the sixteen questions of the course.

    A chip works when it does what was intended, in every situation it will meet. Nobody can try every situation, so verification never proves a design correct; it gathers enough evidence, cheaply enough and early enough, that the remaining risk is acceptable.

    This part sets up the whole course: the difference between verification, validation and test, why a late bug costs so much more than an early one, why exhaustive simulation is impossible even for small blocks, and the project you will verify throughout, DCRouter and its 24 planted bugs.

    After this part you can

    • Explain the difference between verification, validation and manufacturing test.

    • Show with numbers why exhaustive simulation is impossible.

    • Describe verification as evidence against risk, not proof of correctness.

    Lessons

    #

    Lesson

    Level

    Status

    0.1

    Verification, Validation and Test

    F · Foundation

    Ready

    0.2

    The Cost of an Escape

    F · Foundation

    Ready

    0.3

    Intent, Design and Implementation

    W · Working

    Ready

    0.4

    You Cannot Test Everything

    W · Working

    Ready

    0.5

    Confidence, Not Proof

    W · Working

    Ready

    0.6

    The Verification Stack

    W · Working

    Ready

    0.7

    Meet DCRouter

    F · Foundation

    Ready

    —

    Drills and checkpoint

    all levels

    Ready

    Every lesson in this part is ready. Work through them in order: each one sets up the problem the next one solves.

    Tip

    DCRouter in this part. Step 1: build and run a smoke test of the bug-free DCRouter. DCRouter is the small router you verify across the course, with 24 planted bugs; see Meet DCRouter.

    Where other courses go deeper

    This course teaches the decisions behind verification. These lessons teach the tools and syntax that carry them out, so this part links to them instead of repeating them.

    • UVM course: Start Here

    • SystemVerilog course: Foundations

    Related topics

    • Course hub

    • Next: Part 1 · What Can Go Wrong

    PreviousNext: Verification, Validation and Test

    Up next

    Up nextVerification, Validation and Test

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • How to Use This Course
    • Reading Paths
    • Concept Map