Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
Some questions need billions of cycles (OS boot, driver workloads, long random runs); whole-chip simulation is far too slow.
Profile, then simulate less design, do less work per cycle, run fewer cycles per question, and parallelise.
Emulation for boot, bring-up and debug with visibility; prototypes for long, fast software runs and real peripherals on stable RTL.
Real timing, memories, analogue and power behaviour, and it adds artefacts of its own; it also shows little of the inside.
On a virtual platform of register- and function-accurate models, then hybrids with real RTL for new blocks.
Detect early with synthesised assertions, capture trace windows around triggers, log transactions, checkpoint, and replay in simulation.
The cheapest that answers the question in time, by cycles, accuracy, visibility, turnaround and availability.
Task. A camera SoC has an image pipeline, a DDR controller, a USB device port and an ARM-class processor running Linux. Tape-out is in nine months. Assign platforms to these goals and say when each becomes possible: verify the pipeline's filters; bring up the USB driver; boot Linux; measure frame rate at 4K; check behaviour at low voltage.
Pipeline filters: block simulation against a bit-accurate C model, with formal on the control logic; from RTL availability. USB driver: virtual platform with a USB device model from the specification stage, then a hybrid with the USB RTL in simulation or emulation once it exists, then the FPGA prototype with a real host cable. Linux boot: virtual platform early for software, emulation once the full RTL compiles (around RTL freeze minus three months), FPGA prototype for software teams afterwards. 4K frame rate: an architecture performance model early for expectations, emulation with real frames for measurement, prototype for long runs; confirm on silicon. Low voltage: only silicon (characterisation, Part 11), prepared by running the same test programs earlier on emulation so they are ready on day one.
About 58 days and about 83 minutes.
Each test runs on one machine; parallelism raises throughput only.
Fewer randomize() calls (about 4,500 instead of 21,000).
The emulator waits for the host on every cycle the testbench exchanges signals.
A synthesisable driver or monitor that converts transactions from the host into cycles on the emulator.
A crossing or delay between FPGAs that the real chip does not have.
The virtual DMA completed instantly; the real one took time and the driver assumed instant completion.
A synthesised assertion, such as DCRouter's R13 wake check, firing at the cycle the rule breaks.
Re-running the billions of cycles before the failure for each attempt.
Silicon.