Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
    • Caches and Shared Data
    • Permissions and Values
      • Permission Versus Data
      • Who Has the Newest Data?
      • Dirty Responsibility
      • Epochs and Serialization
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
Loading lesson

‹Permissions and Values
  1. Topics
  2. Cache Coherency
  3. Why Coherence Exists
  4. Permissions and Values
  5. Epochs and Serialization

Part 1 · Why Coherence Exists · All levels

Epochs and Serialization

Identify read and write epochs and follow an upgrade that waits for invalidation acknowledgement before granting a writer.

On this page

    When does a reader become a writer?

    A store request is an intention, not permission. A read epoch allows read-only copies and has no active writer. A write epoch gives one cache exclusive permission; it may contain many local loads and stores without any new coherence transaction. Idle time with readers remains a read epoch. There need not be a writer somewhere in the machine at every instant.

    The value entering a new epoch must carry forward the result of the preceding write epoch, or the initial value if no write has occurred. Equal permissions alone cannot ensure this. The Primer, second edition, Chapter 2 develops the SWMR and data-value invariants using epochs. We apply that reasoning to one location, X; it does not establish ordering between different addresses or language-level synchronization.

    An upgrade changes permission without a refill

    For this independent warm example choose MSI: C0 and C1 start S / 0, H is S{C0,C1}, and memory = 0. This is a reachable read-epoch snapshot of the initially uncached X = 0. No earlier writer is assumed. C0 already has the correct data, so the final Data is permission-only: it authorises M while keeping the cached value 0. H serializes conflicts for X, records this upgrade as pending at step 1, and collects C1's Inv-Ack at step 3 before sending the step-4 grant: four serial legs.

    C0 sends GetM to H, H invalidates C1, C1 acknowledges to H, and H grants M in permission-only Data before C0 stores 1.
    An MSI upgrade: four messages and one local store; permission arrives only after the required acknowledgement.

    Step

    C0 state / value

    C1 state / value

    H directory

    Memory

    Newest data

    0. Read epoch

    S / 0

    S / 0

    S{C0,C1}

    0

    C0, C1 and memory: 0

    1. GetM at H

    SM^D / 0

    S / 0

    S{C0,C1}, pend GetM C0, acks 0/1

    0

    C0, C1 and memory: 0

    2. Inv at C1

    SM^D / 0

    I / -

    S{C0,C1}, pend GetM C0, acks 0/1

    0

    C0 and memory: 0

    3. Inv-Ack at H

    SM^D / 0

    I / -

    S{C0}, pend GetM C0, acks 1/1

    0

    C0 and memory: 0

    4. Data at C0

    M / 0

    I / -

    S{C0}, pend GetM C0, acks 1/1

    0

    C0 and memory: 0, Data carried no value

    (assumed) grant delivered

    M / 0

    I / -

    exclusive(C0)

    0

    C0 and memory: 0

    L. Local store

    M / 1

    I / -

    exclusive(C0)

    0

    C0: 1

    In SM^D C0 keeps its S copy: loads hit, stores stall. M / 0 at step 4 is deliberately conservative: the cache has write permission and takes dirty responsibility even before the pending store executes. At step 2 the directory still lists C1 until H processes its acknowledgement, although C1 has already invalidated. Pending metadata records outstanding obligations rather than a perfect instantaneous inventory. Likewise H keeps the pending upgrade in the step-4 row and records exclusive(C0) only in the '(assumed) grant delivered' row.

    Serialization is a decision backed by completion

    H chooses this upgrade before any conflicting transaction for X, then holds later work until it completes. The choice and the usable write grant are different events: selecting C0 does not revoke C1's permission. C1 loses its readable copy at step 2; H learns that at step 3; C0 can use exclusive permission at step 4. Those causal dependencies, not any assumed message order, make the boundary safe.

    Common pitfall

    Do not grant on 'Inv sent' or merely because C0 already has value 0. Until the required Inv-Ack reaches H, C1's invalidation is unconfirmed. An early write could overlap a permitted old read. Data equality is no substitute for excluding readers.

    Check yourself At step 3, both C0 and memory hold 0 and C1 is invalid. Has C0's write epoch begun?

    Not yet in this teaching trace. H has completed its acknowledgement wait, but C0 is still in SM^D until the permission-only Data arrives at step 4. The exclusive grant begins the usable write epoch; L changes the value within it.

    Interview

    Name three points when drawing an upgrade: H selects the transaction, the last required acknowledgement arrives at H, and the requester receives usable write permission. Then show the local store as a note labelled L, not a new opcode. This makes the permission boundary explicit.

    Related topics

    • Course Model

    • Permission Versus Data

    • Up: Permissions and Values

    Previous

    13 / 167

    Next: States and Protocols

    Up next

    Up nextStates and Protocols

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Permission Versus Data
    • Who Has the Newest Data?