Because they narrate events in arrival order and hope the listener follows. A race is not a sequence; it is two transactions that both want X and a rule that orders them. Explain the rule, and the sequence follows. The course's routine has four steps, each with a question you must answer out loud.
Step | Question to answer | Typical weak version |
|---|---|---|
1. Name | Which two transactions, from which caches, with what request type and starting snapshot? | "Two requests collide." |
2. Serialize | At which node and which event is the order decided? What did the loser's cache do before it knew it lost? | "Whichever arrives first." (First where, at what event?) |
3. Wait or retry | Is the second transaction queued at H, NACKed and retried, or overtaken so that it arrives after its state is gone? What state is its requester in meanwhile? | "It retries." (Who keeps it, what bounds the retries?) |
4. Data safety | At every step, which places hold the newest value, and which rule stops the value being lost or overwritten? | "The protocol handles it." |
Trace: Simultaneous Upgrades. Roles kept: C0's GetM is A and wins, C1's GetM is B and waits. Start C0 S / 0, C1 S / 0, H S{C0,C1}, memory = 0, MSI, acks at H.
Step | Explanation on this race |
|---|---|
1. Name | A: C0 GetM, upgrade from S. B: C1 GetM, upgrade from S. Both caches are in SM^D: loads hit, stores stall. |
2. Serialize | H accepts A first; that acceptance orders A before B for X. Before learning that it lost, C1 already sent B, and it still holds S / 0. |
3. Wait | B is queued at H, not NACKed. C1 must still answer A's Inv while B waits: it goes SM^D to IM^D, keeps its store pending and acks. Refusing the Inv until B completes would make A wait for C1 while B waits for A. |
4. Data safety | C0 receives permission-only Data and stores 1. For B, H forwards to C0, C0 sends Data(1) to H, H sends Data(1) with M to C1. B needs data, not permission only, because C1's copy was invalidated. Memory stays 0, legal because C1 ends as the dirty exclusive holder. |
Spoken version: "A and B are both upgrades. H accepts A first, so B queues. C1 loses its copy to A's Inv while still wanting to write, so when B is served it needs the value 1, which H gets from C0 by a forward. C0 stores before answering the forward, so there is no ping-pong. Two writes, ordered 1 then 2, never two writers."
Trace: Eviction Versus Intervention. Roles kept: W is C0's PutM writeback of 1, R is C1's GetS. C0 has moved 1 into its writeback buffer and is in MI^A; H still records exclusive(C0), memory = 0, MSI. The lesson shows both orders; the explanation names which order it is describing.
Step | Order A: W first | Order B: R first |
|---|---|---|
1. Name | W: C0 PutM(1). R: C1 GetS. | Same transactions. |
2. Serialize | H accepts W before R arrives. | H accepts R while W is still in flight. |
3. Wait or overtaken | R is queued behind W. H writes memory, sends Put-Ack to C0, then serves R from memory. | Nobody waits for W. H forwards to C0, which answers from its writeback buffer and goes to SI^A. W arrives after R has completed, from a cache H no longer records as a holder: Put-Ack, no change to the directory or memory. |
4. Data safety | The value is in C0's writeback buffer and H's buffer until memory holds 1; C0 frees the buffer only on Put-Ack. | The writeback buffer, not the cache array, supplies 1. H writes memory before granting R. The late PutM must not be treated as a normal writeback, or it could erase C1's sharer record. |
Order B also shows why the ordering assumption belongs in the explanation. C0 sent PutM W before it received the forward, yet its Data for R reaches H first. That is possible because the course assumes no FIFO order between the same two nodes. With point-to-point FIFO from C0 to H, R could still win, but W's PutM would reach H before C0's Data, while R is still pending, and H holds W in X's pending entry until the forward is answered (Rule 2 of A Power-Down Race). Say which assumption you are using.
Every race explanation should end with one sentence of this form: "The newest value is always in X, Y or Z, and rule R stops it being overwritten." For race 1: in C0, then Data(1) in flight, then H's buffer, then C1, and the store-before-forward rule plus H's queue keep one writer at a time. For race 2: in C0's writeback buffer until Put-Ack, and the late-PutM rule stops a stale writeback. If you cannot write that sentence, the race is not explained yet.
It is a different design, not an error, but it changes steps 3 and 4. The answer must say C1 keeps B and retries, that C1 still answers A's Inv in the meantime, and what bounds the retries (a fairness or priority rule), because unbounded retry can starve C1. See Retries, NACKs and Credits and Fairness on a Contended Line.
C0 had already evicted the line: it answers from the writeback buffer and enters SI^A, which serves no loads. Its Data tells H that a PutM is outstanding, so H does not count C0 as a sharer. The final sharer set is {C1}.