C0 issues a load, but its cache is I for X. Finding 0 in memory is not enough: the cache also needs permission to use that value. Review the permission distinction if data arrival and permission sound interchangeable.
Trace: The Course Model in Action, steps 1 and 2 (MSI), and Caches, Lines and Write-Back (MESI). Same roles: C0 reads from the initial state (both caches I, H U, memory = 0). C0 sends GetS, waits in IS^D, H reads memory = 0 and returns Data. The new question here is which grant that Data carries.
IS^D means 'was I, wants S, waiting for Data': no load can complete yet. The load completes only when Data reaches C0, which then holds both the value and the permission. Memory may answer because H shows U: no cache holds X, so memory has the newest value. If H recorded an exclusive or dirty-responsible holder, it would have to ask that holder first.
MESI changes only the grant. H sees no other holder and returns E instead of S. Everything else in the trace is identical.
Case | Grant at step 2 | H directory after | C0's first store |
|---|---|---|---|
MSI | Data(X=0, S) | S{C0} | Needs a second transaction: GetM, then Data(M) |
MESI | Data(X=0, E) | exclusive(C0) | Hits: E becomes M silently, no message |
E saves a whole transaction when a lone reader writes next, which is common for private data. The price is that H must now treat C0 as an exclusive holder: a later reader cannot be served from memory alone, because C0 may have written silently. Who May Supply Data? shows why H must forward even when the E copy is still clean.
No. Its granted state is S. The absence of another copy is not permission for a silent upgrade; it must send GetM. Only MESI's E grant allows the silent store.