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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
    • Read and Write-Permission Flows
      • Cold Read Miss
      • Read of a Shared Line
      • Write Miss and Ownership
      • Upgrade from Shared
    • Forwarding Versus Memory Sourcing
    • Writeback, Eviction and Cleaning
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Read and Write-Permission Flows
  1. Topics
  2. Cache Coherency
  3. Transactions
  4. Read and Write-Permission Flows
  5. Write Miss and Ownership

Part 3 · Transactions · All levels

Write Miss and Ownership

Follow the basic write misses: from U, where memory supplies the value, and from a shared line, where H must invalidate the reader first.

On this page

    Ownership in this title means exclusive write permission: the M state, granted by H.

    What does a write miss need?

    A store to one field does not replace every byte in its 64-byte line. A write-allocate miss therefore needs both exclusive permission and the current line contents. The traces show one value X, but Data carries the whole line.

    Two basic cases differ only in what H must do before it can grant M: nothing, or invalidate the readers. A third case, where another cache holds the line dirty, is the exclusive-permission transfer of Three-Hop Versus Four-Hop.

    From U: memory supplies the value

    With H showing U, the write miss is the cold write traced in SWMR Precisely: 1. GetM, H reads memory, 2. Data(X=0, M). C0 waits in IM^D ('was I, wants M, waiting for Data'), cannot load or store, and enters M when Data arrives. Two legs, no other cache involved.

    From S{C0}: invalidate the reader first

    Trace: The Course Model in Action, steps 3 to 6 and L (MSI). Same roles: from the checkpoint C0 S / 0, C1 I / -, H S{C0}, memory = 0, C1 wants to store 1. C1 has no copy, so it needs the value as well as M, and C0's read copy must go before C1 may write. C1 sends GetM and waits in IM^D, H sends Inv to C0, C0 answers Inv-Ack to H, H reads memory = 0 and grants Data(X=0, M), then C1 stores 1.

    After the Inv-Ack the sharer set is empty, but H is still busy with C1's GetM, so it is not free for another request. Memory is current throughout, because S copies are clean in MSI.

    H may read memory while it waits

    Part 1 draws the memory read after the Inv-Ack, but nothing forces that order. H may start the memory read as soon as the GetM arrives and overlap it with the Inv round trip. That hides the memory latency, not the ack round trip: H must not send Data before the Inv-Ack, because with no FIFO order C1 could store while C0 still reads 0.

    Compare the two cases: from U the miss costs two legs, from S{C0} four, and the extra two are the Inv round trip. The value comes from memory in both, because no cache holds it dirty. If C0 held M, H would forward instead, as the three-hop lesson shows.

    Common pitfall

    Counting the Inv as done when H sends it. Only the Inv-Ack shows that C0 has stopped reading. Granting M before it arrives lets a writer and a reader overlap.

    Interview

    For any write miss, list what H must clear before granting M: nothing (U), every sharer (S), or the exclusive holder (forward). Then count the serial legs.

    Check yourself Why does C1's write miss from S{C0} need Data from memory while C0's upgrade in the next lesson does not?

    C1 has no copy, so it needs the line's bytes as well as permission. In the upgrade the requester already holds a valid S copy, so H sends permission only.

    Related topics

    • Shared course model

    • Trace: The Course Model in Action

    • Compare: upgrade without a refill

    • Dirty-holder case: exclusive-permission transfer

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    See also

    • Cold Read Miss