The dirty read with C0 in M was traced in Who Has the Newest Data? under MESI, and the messages are the same in MSI (MSI Protocol): GetS, Fwd-GetS, Data to H, H writes memory, Data to C1. This lesson asks two new questions: what changes when the holder is a clean E copy, and what changes when C0 sends Data straight to C1.
Start from the MESI cold read of Caches, Lines and Write-Back, before its local store: C0 E / 0, C1 I / -, H exclusive(C0), memory = 0. C0 has not stored. C1 sends GetS.
Step | C0 state / value | C1 state / value | H directory | Memory | Newest data |
|---|---|---|---|---|---|
Checkpoint | E / 0 | I / - | exclusive(C0) | 0 | C0 and memory: 0 |
1. GetS at H | E / 0 | IS^D / - | exclusive(C0), pend GetS C1 | 0 | C0 and memory: 0 |
2. Fwd-GetS at C0 | S / 0 | IS^D / - | exclusive(C0), pend GetS C1 | 0 | C0 and memory: 0, Data(0) in flight to H |
3. Data at H | S / 0 | IS^D / - | exclusive(C0), pend GetS C1 | 0 | C0, memory and H buffer: 0 |
H writes memory | S / 0 | IS^D / - | S{C0}, pend GetS C1 | 0 | C0 and memory: 0, Data(0) in flight to C1 |
4. Data at C1 | S / 0 | S / 0 | S{C0}, pend GetS C1 | 0 | C0, C1 and memory: 0 |
(assumed) grant delivered | S / 0 | S / 0 | S{C0,C1} | 0 | C0, C1 and memory: 0 |
The messages are exactly those of the M case. C0 replies with Data whether it is E or M, and H writes that Data to memory before recording S{C0} (S claims memory is current), and settles S{C0,C1} once the grant is delivered. For a clean line the write leaves memory's value unchanged, but H cannot know the line was clean, so this course always writes. That single rule is correct in both cases.
Case | C0 at Fwd-GetS | Data to H | Memory write | Ends |
|---|---|---|---|---|
MESI, E holder | E / 0 becomes S / 0 | Data(X=0) | Writes 0, value unchanged | S / 0, S / 0, memory = 0 |
MSI or MESI, M holder | M / 7 becomes S / 7 | Data(X=7) | Writes 7, needed | S / 7, S / 7, memory = 7 |
A protocol could let a clean holder say 'clean, no data' and have H use memory instead. That saves a data transfer but needs a separate reply type; this course keeps one reply for both.
Now let C0 hold M / 7 and send Data directly to C1, with a second copy to H for memory. C1 gets its value one leg earlier, but the memory write is still owed: settled MSI S/S requires memory = 7. Start from C0 M / 7, C1 I / -, H exclusive(C0), memory = 0.
Step | C0 state / value | C1 state / value | H directory | Memory | Newest data |
|---|---|---|---|---|---|
Checkpoint | M / 7 | I / - | exclusive(C0) | 0 | C0: 7 |
1. GetS at H | M / 7 | IS^D / - | exclusive(C0), pend GetS C1 | 0 | C0: 7 |
2. Fwd-GetS at C0 | S / 7 | IS^D / - | exclusive(C0), pend GetS C1 | 0 | C0: 7, Data(7) in flight to C1 and to H |
3. Data at C1 | S / 7 | S / 7 | exclusive(C0), pend GetS C1 | 0 | C0 and C1: 7, Data(7) in flight to H |
4. Data at H | S / 7 | S / 7 | exclusive(C0), pend GetS C1 | 0 | C0, C1 and H buffer: 7 |
H writes memory | S / 7 | S / 7 | S{C0}, pend GetS C1 | 7 | C0, C1 and memory: 7 |
(assumed) grant delivered | S / 7 | S / 7 | S{C0,C1} | 7 | C0, C1 and memory: 7 |
Messages 3 and 4 leave C0 together and may arrive in either order; the table shows one order. Between step 3 and the memory write the two caches hold S / 7 while memory still holds 0. That is not a settled MSI state, so H keeps the transaction pending and must not serve any new reader from memory until the write is done. As on the course-model page, the model assumes H can tell when C1 has received its Data.
MOESI avoids the memory write altogether by leaving C0 in O / 7 with C1 S / 7 and memory = 0; see Dirty Responsibility. That is a different protocol, not a way to skip the write in MSI.
Memory still holds 0 and the copy of 7 for memory is still in flight to H. H must write memory, and learn that C1 has its Data, before it records settled S{C0,C1}.