Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the lessons linked at the end.
It is lost; the requester waits for ever unless a timeout, a reset-aware wrapper, quiescing or a joint reset handles it.
Requests into a target in reset are dropped and the master hangs; make start-up order-independent with an explicit readiness signal.
Mark the device gone, complete every outstanding request with an error, free its resources, and let software recover.
To find bits, symbols and lane order and tune equalisation to the channel before data can be decoded.
Each advertises its abilities and both take the highest common setting by the same rule; fall back if it fails to train.
Write all 1s, read back; the bits that stay 0 give the window size.
No; packets wait, but state is kept and traffic resumes without loss.
Senders set them to 0; receivers ignore them.
Task. Specify start-up for a chip-to-chip link between two chips from different vendors, each with a different maximum speed and lane count, either of which may be reset or powered down independently. Cover reset behaviour, readiness, training, negotiation, the link state machine, and what happens to traffic when one side resets.
Reset: each side drives inactive outputs and sends nothing but training patterns until its link state machine reaches ACTIVE. States: DOWN, TRAINING (lock, deskew, equalise), INIT (credits and sequence numbers), ACTIVE, RECOVERY, LOW POWER, each with a timeout back to DOWN. Negotiation: training words carry a version, highest speed, lane count and feature bits; each side takes the minimum speed, minimum lanes and intersection of features, accepted only after several matching words; reserved bits set to 0 and ignored. Fallback: if the agreed setting fails to train, retry at the next lower speed or width. Order independence: no packets until credits are granted, so whichever side leaves reset first simply waits. One-sided reset: the partner sees training patterns or loss of lock, goes to DOWN, completes every outstanding request with an error, discards credits and replay state, and retrains; requesters also keep completion timeouts. Debug: expose the link state, time in each state and recovery counts.
Inactive values: no valid signals, no requests.
Separate per-domain synchronisation; waiting for PLL lock, calibration or firmware.
No credits, no sending: the sender waits for the receiver's initial credits.
Orderly drains first; surprise leaves requests in flight that must be failed with errors.
Symbol boundaries can only be found in correctly recovered bits.
Each board's channel distorts differently and changes with temperature.
Speed 1, 2 lanes.
The host enumerates one at a time, moving each to a unique address.
So both ends leave together; local timers drift apart.
The old side, by having ignored reserved and unknown content from version 1.