Two chips are connected by a 16-lane link at 16 gigatransfers per second. At power-up, each receiver sees a fast, distorted stream of edges: it does not know where the bits are, where the symbols begin, which lane is which, or how badly the channel smears each bit into the next. Sending real data now would produce garbage. First the two sides have to rehearse.
Why must a high-speed link train before it carries data, and what happens during training?
The obvious link starts sending data as soon as it powers up. Slow, parallel, clock-forwarded buses can do that. A fast serial link cannot: its receivers recover the clock from the data (lesson 1.4), must find symbol boundaries in an unbroken stream (lesson 2.8), and must compensate for a channel that distorts differently on every board. None of that is known in advance. It has to be learned from a known pattern, sent before any data.
Stage | Learns | How |
|---|---|---|
Detect | Is anything connected on each lane? | Electrical detection of a receiver's termination |
Bit lock | Where the bits are (clock recovery) | A transition-rich pattern lets each receiver's CDR lock |
Symbol or block lock | Where symbols or blocks begin | Known alignment patterns in training sequences (lesson 2.8) |
Lane alignment and deskew | Which lane is which, and how to line them up | Training sequences carry lane numbers; common markers remove lane-to-lane skew |
Equalisation | How to undo this channel's distortion | The receiver measures quality and asks the sender to adjust its transmit filter, iterating |
Configuration | Width, speed and features both support (lesson 11.5) | Capabilities exchanged in the training sequences |
At high rates, each bit's energy spreads into its neighbours (inter-symbol interference), and how much depends on the trace length, connectors, vias and materials of that particular board. No fixed setting suits every board. So the sender and receiver tune it together: the receiver measures how open the signal's eye is, asks the sender for a different pre-emphasis setting, measures again, and settles on the best. Faster generations spend more training time on this step.
Protocol | Training |
|---|---|
PCI Express | The LTSSM: Detect (find a receiver), Polling (bit and symbol lock, exchanging TS1 and TS2 ordered sets), Configuration (width and lane numbering) to L0; Recovery retrains and changes speed, and from Gen3 includes equalisation phases. |
High-speed Ethernet | Auto-negotiation and link training on backplane and copper links, including transmitter equalisation adjustment. |
DCLink | Training words carry capabilities (step 10); lock and alignment are lesson 2.8's mechanisms. |
A board (illustrative) trained reliably at room temperature and sometimes failed to reach the active state in a hot chamber. The equalisation settings found at power-up were marginal as the channel's loss rose with temperature. Allowing the link to re-run equalisation in its recovery path, instead of only at power-up, kept it up across the temperature range.
Symbol boundaries can only be found in a stream of correctly recovered bits; without bit lock, there are no reliable bits to search.
A transient loss of lock can be fixed by relocking and retuning without the full sequence from detection, so the link is back in service sooner.
Fast serial links must learn bit boundaries, symbol boundaries, lane order and channel equalisation before carrying data.
Training proceeds in stages, each building on the last, and ends by agreeing configuration.
Expose training state for debug; a recovery path retrains an active link without starting over.