Read across for one protocol; read down to see how differently each one gets from power-up to its first transaction.
PCI Express | USB | Ethernet | AXI | DCLink | |
|---|---|---|---|---|---|
Reset rule | Link reset retrains and re-initialises flow control | Port reset before enumeration | Link restarts auto-negotiation | Valids low in reset; start on a clock edge after ARESETn is high | Training and credits before any packet |
Partner detection | Receiver detection; slot presence detect | Attach detected per port | Link pulses / signal detect | None (fixed wiring) | First training word |
Training | LTSSM: Detect, Polling, Configuration, L0; Recovery with equalisation | Speed detection and handshake | Auto-negotiation; link training on backplanes | None | Lesson 2.8 lock, then step 10 |
Negotiation | Rates in TS1/TS2; width in Configuration | Highest common speed and version | Highest common mode | Optional signals with defaults | Minimum speed and lanes, confirmed twice |
Enumeration | Config space scan, bus numbers, BAR sizing | Default address 0, descriptors, SET_ADDRESS | — (addresses at higher layers) | Fixed address map | — |
Hot-plug | Slot hot-plug, optional surprise removal | Native | Native (cable) | Power domains with isolation | — |
Evolution | Capability lists, fallback to older rates | Version in descriptors | Negotiated modes | Optional signals, defaults | Room for version and feature bits |
Off-chip links must discover, train and negotiate, because neither side knows what it will meet.
On-chip buses mostly skip it: the wiring and address map are fixed at design time, so reset rules carry the burden.
Enumeration appears wherever devices can be added, and always needs a default way to reach a new one.
Compatibility rules are the oldest part of each protocol, set in its first version.