An interviewer slides a blank grid across the table: ten protocols down the side, six questions across the top. "Fill in what you can, then tell me why any two rows differ." Filling the grid tests recall; explaining it tests whether you understand that every cell follows from a constraint.
Can you fill the matrix from memory and explain each difference?
Protocol | When is data valid? | Is the receiver ready? | How much may I send? | How many in flight? | What if bits go wrong? |
|---|---|---|---|---|---|
UART | ? | ? | ? | ? | ? |
SPI | ? | ? | ? | ? | ? |
I2C | ? | ? | ? | ? | ? |
APB | ? | ? | ? | ? | ? |
AHB | ? | ? | ? | ? | ? |
AXI4 | ? | ? | ? | ? | ? |
PCI Express | ? | ? | ? | ? | ? |
DDR | ? | ? | ? | ? | ? |
Ethernet | ? | ? | ? | ? | ? |
USB | ? | ? | ? | ? | ? |
Fill all fifty cells (ten protocols, five questions each) on paper before checking. Then pick three pairs of rows and explain every difference between them using the five constraint questions (distance, bandwidth and latency, wires, topology, who builds each side).
Timing: No clock; start bit re-aligns. Ready: None. Flow control: None in the frame. In flight: One character. Errors: Parity, framing error; no retry. Details on the UART page.
Timing: Master's clock. Ready: None. Flow control: Master paces. In flight: One transaction. Errors: None. Details on the SPI page.
Timing: Master's clock; stable while SCL high. Ready: ACK per byte; clock stretching. Flow control: Per byte. In flight: One transaction. Errors: Missing ACK only. Details on the I2C page.
Timing: Common clock. Ready: PREADY wait states. Flow control: One transfer. In flight: One. Errors: PSLVERR. Details on the APB page.
Timing: Common clock. Ready: HREADY wait states. Flow control: One data phase. In flight: Pipeline of two. Errors: Two-cycle ERROR. Details on the AHB page.
Timing: Common clock. Ready: VALID/READY per channel. Flow control: READY back-pressure. In flight: Many, by ID. Errors: SLVERR/DECERR; no retry. Details on the AXI4 page.
Timing: Embedded clock, CDR. Ready: Credits. Flow control: Six credit types. In flight: Many, by tag. Errors: LCRC + replay; ECRC; FEC (Gen6). Details on the PCI Express page.
Timing: Strobes (DQS). Ready: None: fixed latency. Flow control: Controller owns timing. In flight: Many banks. Errors: ECC DIMMs. Details on the DDR page.
Timing: Embedded clock. Ready: None per frame. Flow control: Lossy; PAUSE/PFC optional. In flight: Many frames. Errors: CRC-32 then drop; FEC. Details on the Ethernet page.
Timing: Recovered from transitions. Ready: ACK/NAK/STALL to host tokens. Flow control: NAK. In flight: One per bus (USB 2.0). Errors: CRC + retry; DATA0/1. Details on the USB page.
Pair | The difference | The constraint behind it |
|---|---|---|
APB and AXI4 | One transfer versus many outstanding by ID | AXI faces long, variable memory latency (C2); APB serves slow registers |
AXI4 and PCI Express | Ready versus credits; no retry versus replay | PCIe's round trip is long and its channel lossy (C1, C2); on-chip wires are short and reliable |
PCI Express and Ethernet | Lossless with replay versus lossy with end-to-end recovery | Ethernet spans networks of any size and leaves delivery to the end points; PCIe must look like a bus to software (C4, C5) |
Recall: 42 or more of 50 cells correct is strong; below 33, revisit the Part 16 pages.
Reasoning: each explained difference must name a constraint; "it's a different protocol" scores nothing.
Reference: the filled-in comparison across fourteen protocols is on Protocols Compared: Protocols Dissected.
Every cell in the matrix follows from a protocol's constraints.
Recall the cells, but practise explaining the differences between rows.
Rows to revisit: UART, AXI4, PCI Express are the ones most often asked about.