A processor issues sixteen reads to DRAM before the first returns, while a DMA engine streams writes through the same interconnect. On AHB, each would wait for the one before it. AXI4 lets them all be in flight at once: requests and responses travel on separate channels, each tagged with an ID, and responses return in whatever order the memory finishes them, as long as each ID's responses stay in order.
How does AXI4 answer each question, and why did those answers win?
Constraint | AXI4 |
|---|---|
C1 Distance and medium | On-chip wires, through interconnects and register slices |
C2 Bandwidth and latency | High bandwidth with long, variable latencies (DRAM), so many transactions must overlap |
C3 Wires | Wide parallel channels; wires are cheap on chip |
C4 Topology | Point-to-point interfaces joined by interconnects with many managers and subordinates |
C5 Who builds each side | Many IP vendors; one Arm specification; IP must interoperate without negotiation |
Each answer links to the lesson that explains the idea behind it.
# | Question | Answer |
|---|---|---|
1 | When is the data valid? | A common clock, ACLK (1.1) |
2 | Where does a message start and end? | A burst's address is sent once; data beats follow on W or R, with WLAST and RLAST marking the last (fact A12) (5.8) |
3 | Is the receiver ready? | VALID/READY on every channel; VALID must not wait for READY and, once high, holds until the transfer (facts A1, A2) (3.3) |
4 | How much may I send before I hear back? | READY back-pressure on each channel, hop by hop; no credits (4.1) |
5 | What exactly is being asked? | Reads and writes in bursts (INCR up to 256 beats, WRAP, FIXED), byte strobes, exclusive access, attributes; bursts must not cross 4 KB (facts A5, A13 to A16, A31) (5.6) |
6 | How many requests can be in flight? | Many outstanding transactions, distinguished by ID (6.4) |
7 | In what order do results become visible? | Same ID: responses in order. Different IDs: any order. No ordering between reads and writes (fact A20) (7.7) |
8 | Who gets the wire? | Interconnects arbitrate per channel; AxQOS hints priority (8.7) |
9 | Why can it hang? | Channel dependency rules (a subordinate must not assert BVALID until both the AW handshake and the last W beat, WLAST, have completed; a manager never waits for READY before VALID) prevent handshake deadlocks (facts A3, A21) (9.3) |
10 | What if bits go wrong? | SLVERR and DECERR responses; no detection or retransmission (facts A6, A11) (10.7) |
11 | How do the two sides agree at start-up? | Reset rules: valids low in reset, start after ARESETn rises; no discovery (fact A24) (11.1) |
12 | How do we save power without losing data? | Not in AXI itself; AMBA's Q-Channel and P-Channel handle power handshakes (fact A22) (12.4) |
13 | What if there are several copies of one value? | Not coherent; ACE and ACE-Lite add coherence and I/O coherence (fact A23) (13.7) |
14 | Who is allowed to ask? | AxPROT: privileged, non-secure, instruction (fact A27) (14.1) |
15 | How do we know it is correct? | Arm protocol assertions and widely used VIP; per-ID scoreboards (fact A29) (15.3) |
Independent channels: reads and writes, requests and responses never block each other at the interface.
IDs: many outstanding transactions, with ordering only where the requester asks for it (same ID).
Register-slice friendly: valid/ready on every channel lets interconnects add pipeline stages anywhere without changing the protocol (lesson 3.8).
Errors reported, not recovered: on-chip wires rarely corrupt data, so AXI leaves recovery to the requester.
An interconnect (illustrative) remapped manager IDs to fewer bits to save area and accidentally gave two managers the same internal ID. Their reads were then forced into one in-order stream, and worse, responses for one manager were occasionally routed to the other. A per-ID scoreboard caught the misrouting; ID width and uniqueness through every interconnect is a standard AXI review item.
No: same-ID responses return in order; only different IDs may reorder.
It waits for the write response (B) before issuing the read; AXI does not order reads against writes.
AXI4: five independent valid/ready channels and IDs for many outstanding transactions.
Ordering only within an ID; none between reads and writes; bursts within 4 KB.
Errors are reported (SLVERR, DECERR), never retried; coherence and power are separate AMBA layers.