A server chip has 64 cores, each with private caches, a mesh of routers, and memory controllers at its edges. A core's read miss must find the latest copy of a line wherever it is, without broadcasting to 63 caches, without deadlocking a network full of requests, snoops and data, and without the interconnect's designers knowing in advance how many requests any home will see. AXI's channels cannot express that. CHI turns coherence into messages.
How does CHI answer each question for a large coherent system?
Constraint | CHI |
|---|---|
C1 Distance and medium | On-chip network: meshes and rings of routers |
C2 Bandwidth and latency | Very high aggregate bandwidth; low latency for coherent misses |
C3 Wires | Packetised channels (flits) between network nodes |
C4 Topology | Many request, home and subordinate nodes on a network the protocol does not fix (fact C2) |
C5 Who builds each side | Arm and licensees; processor, interconnect and memory controller IP must interoperate |
Each answer links to the lesson that explains the idea behind it.
# | Question | Answer |
|---|---|---|
1 | When is the data valid? | On-chip clocks, with asynchronous bridges between domains where needed (1.9) |
2 | Where does a message start and end? | Messages carried as flits on four channel types: REQ, RSP, SNP, DAT (fact C2) (2.10) |
3 | Is the receiver ready? | No ready: link-layer credits guarantee a flit can be accepted on each link (fact C1) (4.3) |
4 | How much may I send before I hear back? | Link credits per channel, plus protocol credits granted after a retry (fact C1) (4.6) |
5 | What exactly is being asked? | Coherent and non-coherent reads and writes, dataless ownership requests and atomics, each a message with a TxnID (fact C2) (5.13) |
6 | How many requests can be in flight? | Many outstanding transactions per node, matched by TxnID (6.4) |
7 | In what order do results become visible? | The home node is the point of coherence: it orders all requests to an address (fact C2) (7.3) |
8 | Who gets the wire? | An on-chip network routes messages between nodes; QoS fields guide arbitration (8.9) |
9 | Why can it hang? | Separate channels keep responses, snoops and data from waiting behind requests; a home without tracker space retries a request and later grants a protocol credit, so requests never block the network (fact C1) (9.7) |
10 | What if bits go wrong? | Error responses, plus Poison and DataCheck fields on data (fact C2) (10.8) |
11 | How do the two sides agree at start-up? | Each link is brought up and down by a LinkActive request/acknowledge handshake (fact C2) (11.7) |
12 | How do we save power without losing data? | The LinkActive handshake also takes links down for power saving; system power control uses AMBA's power interfaces (facts C2, A22) (12.4) |
13 | What if there are several copies of one value? | Full coherence: states Unique Dirty, Unique Clean, Shared Dirty, Shared Clean, Invalid; snoops from the home; Direct Cache Transfer between caches (fact A23) (13.5) |
14 | Who is allowed to ask? | Requests carry an NS (non-secure) attribute (fact C2) (14.1) |
15 | How do we know it is correct? | VIP and formal verification of the protocol's state and message tables (15.7) |
Coherence as messages: requests, snoops, responses and data are separate message classes, which scales to networks rather than buses.
Home nodes: one ordering point per address replaces bus ordering and directs snoops only where needed.
Retry with protocol credits: homes never need buffers sized for the worst case, yet requests cannot livelock (lesson 9.8).
Direct transfers: data goes straight from memory or an owning cache to the requester, keeping coherent misses short.
An interconnect implementation (illustrative) let a snoop response share a network virtual channel with new requests. Under heavy load the channel filled with requests, the snoop responses that the home needed to complete earlier transactions could not get through, and the homes could not free tracker entries to accept the requests: a message-dependent deadlock. Giving each message class its own channel and credits, as the protocol's separation intends, removed it.
Homes need the responses to complete transactions and free space for requests; shared buffers full of requests can block the responses, a message-dependent deadlock.
That the home has reserved tracker space, so the retried request will be accepted.
CHI expresses coherence as messages on separate REQ, RSP, SNP and DAT channels over a network.
Home nodes order each address; link credits and retry with protocol credits keep the network deadlock-free.
Direct transfers keep coherent misses short; races between messages are where verification effort goes.