Answer each question out loud before opening it. If you miss more than three in the checkpoint, revisit the protocol pages linked at the end.
Answer the five constraint questions, then each of the fifteen questions: mechanism, alternative rejected, reason, what is left to the system.
Addressing, acknowledgement, arbitration and clock stretching.
With one master per layer there is nobody to hand the bus to; multi-layer interconnects handle several masters.
So reads and writes never block each other and each can have many outstanding transactions; there is no read/write ordering.
Credits prevent overflow (transaction layer); ACK/NAK and replay recover corruption (data link layer).
Fixed latencies keep the DRAM simple and the bus fast; the controller schedules everything.
End to end, from TCP or the application; PFC makes links lossless when needed.
CXL.io (PCIe), CXL.cache (device caches host memory), CXL.mem (host uses device memory).
Task. A new accelerator must attach to a processor. Option A: on the same die, as an AXI4 manager and subordinate. Option B: on a separate card, over PCI Express. Dissect both choices for this use: timing, flow control, concurrency, ordering, errors, bring-up, coherence and security, and recommend one for an accelerator that shares large data structures with the CPU.
AXI4 on die: common clock; READY back-pressure; many outstanding by ID; per-ID ordering, no read/write ordering; errors reported, never retried (fine on chip); no bring-up beyond reset; coherence only with ACE or ACE-Lite (I/O coherence lets it read CPU-cached data without maintenance); AxPROT for security, with an SMMU in its path. PCIe card: embedded clock; credits; many outstanding by tag; producer-consumer ordering table; LCRC with replay; LTSSM training and enumeration; DMA snooped by the host but no device caching (unless CXL); IOMMU via requester ID, IDE if the link is exposed. For shared large data structures, latency and coherence dominate: on die with ACE-Lite (or full coherence) avoids copies and cache maintenance and has far lower latency. If it must be a card, CXL (CXL.cache for coherent access, CXL.mem if the card has memory) answers the coherence question that plain PCIe leaves to software.
The start bit's falling edge.
By its own chip-select line.
Open-drain, wired-AND lines: a 0 wins, and a master reading 0 after sending 1 stops.
Two cycles: setup and access.
None: they may complete in any order.
TID for stream identity, TDEST for routing.
Posted writes must be able to pass non-posted requests and completions.
The home node, the point of coherence.
Each endpoint has only one transaction outstanding.
The physical layer: short-reach, forwarded clock, many lanes.