A processor fetches instructions from on-chip memory. With APB-style two-phase transfers, it would spend half its cycles on setup. AHB overlaps them: while one transfer's data moves, the next transfer's address is already on the bus, so a fast memory can deliver one word every cycle. That single idea, pipelining address and data, defines most of AHB.
How does AHB answer each question, and what does pipelining cost it?
Constraint | AHB |
|---|---|
C1 Distance and medium | On-chip wires |
C2 Bandwidth and latency | One transfer per cycle for fast memories; moderate frequencies |
C3 Wires | Parallel address, read and write data buses, control |
C4 Topology | A shared bus; original AHB with several masters and an arbiter, AHB-Lite with one master (fact A30) |
C5 Who builds each side | Many IP vendors; one Arm specification |
Each answer links to the lesson that explains the idea behind it.
# | Question | Answer |
|---|---|---|
1 | When is the data valid? | A common clock, HCLK (1.1) |
2 | Where does a message start and end? | Each transfer has an address phase and a data phase; HTRANS marks NONSEQ (first) and SEQ (following) beats of a burst, HBURST its length (fact A30) (5.8) |
3 | Is the receiver ready? | The subordinate holds HREADY low to stretch the data phase, which also holds the next address (3.2) |
4 | How much may I send before I hear back? | Implicit through HREADY: the pipeline advances only when the current data phase completes (4.1) |
5 | What exactly is being asked? | Single transfers and bursts (INCR, WRAP4/8/16, INCR4/8/16) with HSIZE and HPROT; bursts must not cross 1 KB (facts A19, A30) (5.10) |
6 | How many requests can be in flight? | One transfer in its address phase and one in its data phase; no outstanding transactions beyond the pipeline (6.3) |
7 | In what order do results become visible? | Strictly in order: a single pipeline (7.1) |
8 | Who gets the wire? | Original AHB: a central arbiter grants the bus (HBUSREQ, HGRANT); AHB-Lite: one master, with multi-layer interconnects for several (fact A30) (8.2) |
9 | Why can it hang? | Original AHB's SPLIT and RETRY let a slow subordinate release the bus; AHB-Lite removed them (fact A7). Locked sequences (HMASTLOCK) hold the bus (fact A18) (9.7) |
10 | What if bits go wrong? | A two-cycle ERROR response on HRESP; no detection or retry of bit errors (facts A19, A30) (10.7) |
11 | How do the two sides agree at start-up? | None: fixed address map and reset |
12 | How do we save power without losing data? | Not addressed by the protocol; clock gating is done by the system |
13 | What if there are several copies of one value? | Not a coherence protocol; HPROT carries cacheable and bufferable hints (5.12) |
14 | Who is allowed to ask? | HPROT carries privilege; AHB5 adds HNONSEC for TrustZone (fact A30) (14.1) |
15 | How do we know it is correct? | Arm protocol checks and VIP; tests cover wait states in bursts, early-terminated bursts, errors and boundary rules (15.6) |
Pipelined phases: address and data overlap, giving one transfer per cycle with simple, in-order logic.
One transfer at a time in the data phase: no IDs, no outstanding transactions, so a slow subordinate stalls everyone behind it.
SPLIT and RETRY, then not: original AHB tried to free the bus during slow accesses with retry-style responses; the complexity was dropped in AHB-Lite, and multi-layer interconnects solved contention instead.
A system (illustrative) placed a slow flash controller on the same AHB-Lite layer as the processor's instruction memory. Every flash access stretched HREADY for dozens of cycles, and the processor stalled on unrelated instruction fetches behind it. Moving the flash to its own layer of a multi-layer interconnect let the two proceed in parallel; AHB's single in-order pipeline cannot overlap a slow access with anything else.
It is held on the bus until the current data phase completes.
It has a single in-order pipeline with no IDs or outstanding transactions.
AHB pipelines address and data phases for one transfer per cycle.
HREADY stretches data phases; bursts, HSIZE and HPROT describe transfers; bursts stay within 1 KB.
One in-order pipeline: simple and fast for one master, but a slow subordinate blocks everyone.