A microcontroller reads a flash memory chip at tens of megabits per second over four wires. It drives the clock itself, pulls the flash's chip-select low, shifts out a command and keeps clocking while the data shifts back. If the flash were absent, the microcontroller would read all ones and never know. SPI is fast because it checks nothing.
How does SPI answer each question, and what does it gain by answering so few?
Constraint | SPI |
|---|---|
C1 Distance and medium | Short: on one board |
C2 Bandwidth and latency | Moderate: up to tens of megabits per second, low latency |
C3 Wires | Clock, data out, data in, plus one chip-select per slave |
C4 Topology | One master, several slaves sharing clock and data lines, each with its own select |
C5 Who builds each side | Many vendors; no single standard, so each device's datasheet defines its commands (fact S11) |
Each answer links to the lesson that explains the idea behind it.
# | Question | Answer |
|---|---|---|
1 | When is the data valid? | The master drives SCLK; data is sampled on one clock edge and changed on the other, chosen by the mode (CPOL, CPHA) (1.1) |
2 | Where does a message start and end? | Chip-select low brackets a transaction; inside it, framing is by bit count as each device defines (2.2) |
3 | Is the receiver ready? | None: the master clocks whenever it wants; the slave must keep up (push, valid-only) (3.6) |
4 | How much may I send before I hear back? | None in the protocol; the master paces everything with the clock, and devices that need time use status polling defined in their datasheet (4.1) |
5 | What exactly is being asked? | Commands, addresses and data are device-specific, defined by each datasheet; SPI only shifts bits (5.4) |
6 | How many requests can be in flight? | One transaction at a time per bus; full duplex shifting both ways at once (6.1) |
7 | In what order do results become visible? | Bits and bytes arrive in the order shifted (7.1) |
8 | Who gets the wire? | The master decides: one chip-select at a time, no arbitration (only one master) (8.1) |
9 | Why can it hang? | Nothing waits for a response, so no deadlock; an absent or busy slave is simply not noticed (9.1) |
10 | What if bits go wrong? | No detection or correction in the protocol; some devices add CRCs or status bits of their own (10.1) |
11 | How do the two sides agree at start-up? | No discovery: the master must know each slave's mode, speed and commands in advance (11.5) |
12 | How do we save power without losing data? | Not addressed by the protocol; deselected devices are idle, and many enter low-power states defined in their datasheets |
13 | What if there are several copies of one value? | Not applicable |
14 | Who is allowed to ask? | Not addressed: access is by physical wiring |
15 | How do we know it is correct? | No compliance programme; verification follows each device's datasheet timing and command set (15.8) |
Master-driven clock: the master sets the pace, so there is no clock recovery and the slave needs no clock of its own.
Selection by wire: one chip-select per slave instead of addresses, trading pins for simplicity.
No acknowledgement: the fastest possible exchange, at the price of never knowing whether anyone listened.
Four modes: clock polarity and phase are configuration both sides must agree on.
A design (illustrative) connected a sensor configured for SPI mode 3 to a master running mode 0. The master sampled on the edge where the sensor was changing data, and readings were occasionally off by one bit position. Nothing reported an error, because SPI has no checks. Setting both sides to the same CPOL and CPHA fixed it; the datasheet had specified the mode all along.
There is one master, and it selects exactly one slave with its chip-select.
Whatever the undriven MISO line floats or is pulled to, typically all ones; SPI cannot tell.
SPI: master-driven clock, one chip-select per slave, full-duplex shifting, no acknowledgement.
Modes (CPOL, CPHA), commands and speeds are agreed in advance from datasheets.
It is fast and simple because it checks nothing; absent or confused slaves go unnoticed.